A novel × 6 frequency multiplier chain with center frequency of 260 GHz is developed in 40 nm CMOS and measured through this work. The multiplication is accomplished through an x3 frequency multiplier followed by a doubler successive stage. A 4-way signal combiner is employed to enhance the output power, whereas phase shifters are dedicated for compensating the possible phase deviations between the different combined ways, and consequently maintain the combining efficiency. For further output power boosting, the output matching network of 260 GHz frequency doubler is optimized, and a stacked amplifier with 11.5 dBm is employed as a driving amplifier. The multiplier has been fabricated and a peak output power of 3.0 dBm is measured at 260 GHz with a 3-dB bandwidth of 17 GHz.

A low-power ultrawideband (UWB) pulse generator based on pulsed oscillator architecture for 3-5 GHz applications is proposed. The pulsed oscillator is improved, so it realizes binary phase shift keying (BPSK) modulation. Unlike ON-OFF keying or pulse-position modulation (PPM), BPSK can scramble the spectrum, so it can be used in high pulse rate applications without having spectral line problem. The signal structure in this design is burst mode of PPM+BPSK. The proposed UWB pulse generator was successfully implemented on 0.18-μm CMOS technology. The peak-to-peak amplitude of output pulse is about 220 mV with 50-Ω load, the maximum power consumption is 4 mW at a raw data rate of 7.8 Mbps and the energy consumption is 32 pJ/pulse at a pulse rate of 125 Mpulses/s.

It is challenging to design high-gain amplifiers near the maximum oscillation frequency (f_max) of the transistors. This paper presents a comprehensive graphical approach to maximize the gain of feedback amplifiers with maximally efficient gain (G_ME) conception at near-fmax frequency. The complex gain-plane and the reflection-coefficient-plane are utilized to provide clear insights into both the gain and stability states of the two-port device while boosting G_ME. An efficient flowchart to synthesize feedback amplifiers is given, which optimizes the G_ME of a two-port device while ensuring the stability. A 210 GHz power amplifier in 40 nm CMOS was designed and optimized based on the proposed approach. The feedback circuit of the transistor pushes it to become potentially unstable and boosts GME. The measured peak small-signal gain was 10.48 dB at 195.33 GHz. The measured saturation output power and large-signal gain at 210 GHz were 3.04 dBm and 7.08 dB, respectively. The presented method could facilitate terahertz amplifier design.

The power gain and output power of millimeter-wave (mm-Wave) and terahertz (THz) amplifiers are critical performance metrics, particularly when the operating frequencies of amplifiers are near to the maximum oscillator frequency ($f_{max}$) of the transistor. This paper presents the design of a 110 GHz amplifier based on the quasi-linear method. The power gain can be boosted to maximum achievable gain ($G_{max}$) using a linear, lossless, reciprocal feedback network, though this leads to a simultaneous decrease in output power. Based on quasi-linear analysis, for an amplifier with $G_{max}$ gain, when the K-factor is equal to 1, the output power is zero. To avoid the very low output power of amplifiers, a new approach is proposed to balance power gain and output power. A 110 GHz six-stage feedback amplifier was designed using the proposed approach and fabricated using 40 nm CMOS technology. The measured power gain is 26.5 dB, and the saturation output power is 13 dBm at 110 GHz.

This paper presents the design and measurements of a 215-252GHz 40nm bulk CMOS frequency doubler with a 6.8dBm deliverable peak output power and a conversion gain of 11.8dB. The designed chip is composed of a 28.5dB gain 6-stages 110GHz power amplifier, an optimized push-push doubler biased in class-C configuration, and an output impedance matching network. A numerical method had been applied here for designing each implemented matching network achieving the optimum matching while maintaining the minimum insertion loss as well. The presented design shows the highest output power among the other sub-THz-designed CMOS counterparts. The design occupies an area of 0.795mm² and shows a total DC power dissipation of 262mW and DC-RF efficiency of 1.87.

This paper presents a 220 GHz × 2 amplifier–doubler chain composed of a rat-race balun, a 6-stage driver amplifier, and a frequency doubler. The presented amplifier–doubler chain was fabricated in commercial 40 nm bulk CMOS technology. The maximum cutoff frequency f_max for the NMOS transistor produced by this manufacturing process was 290 GHz. The saturation output power of the six-stage driver amplifier at 110 GHz was 11.5 dBm. The transistor of the frequency doubler consisted of a single-row interleaved Poly-Diffusion Contact balancing structure. Theoretically, the single-row interleaved Poly-Diffusion Contact balancing structure was able to effectively avoid parasitic components. The simulated results demonstrate that the presented structure achieves a higher output than the conventional designs. Based on these measured results, the presented amplifier–doubler chain provides a peak output power of 7.9 dBm at 200 GHz and a 3-dB bandwidth of 30 GHz. Based on the comparison with other reported results, the presented amplifier–doubler chain provides the highest output power among reported frequency doublers fabricated in CMOS technology.