After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

Short-wave infrared (SWIR) imaging has a wide range of applications in civil and military fields. Over the past two decades, significant efforts have been devoted to developing high-resolution, high-sensitivity, and cost-effective SWIR sensors covering the spectral range from 0.9 μm to 3 μm. These advancements stimulate new prospects across a wide array of fields including life sciences, medical diagnostics, defense, surveillance, security, free-space optics (FSO), thermography, agriculture, food inspection, and LiDAR applications. In this review, we begin by introducing monolithic SWIR image sensors and hybrid SWIR image sensors and indicate that flip-chip bump bonding technology remains the predominant integration method for hybrid SWIR image sensors owing to its outstanding performance, adaptable integration with innovative epitaxial SWIR materials, long-term stability, and long-term reliability. Subsequently, we comprehensively summarize recent advancements in epitaxial thin-film SWIR sensors, encompassing FPAs and flip-chip bump bonding technology for epitaxial InGaAs and Ge (Sn) thin-film SWIR sensors. Finally, a summary and outlook regarding the development of InGaAs and Ge (Sn) SWIR sensors are provided and discussed. The ongoing evolution of epitaxial thin-film SWIR sensors with flip-chip bump bonding technology is poised to foster new applications in both academic and industry fields.

Uncooled microbolometers play a pivotal role in infrared detection owing to their compactness, low power consumption, and cost-effectiveness. This review comprehensively summarizes recent progress in thermistor materials and focal plane arrays (FPAs), highlighting improvements in sensitivity and integration. Vanadium oxide (VO_x) remains predominant, with Al-doped films via atomic layer deposition (ALD) achieving a temperature coefficient of resistance (TCR) of −4.2%/K and significant 1/f noise reduction when combined with single-walled carbon nanotubes (SWCNTs). Silicon-based materials, such as phosphorus-doped hydrogenated amorphous silicon (α-Si:H), exhibit a TCR exceeding −5%/K, while titanium oxide (TiO_x) attains TCR values up to −7.2%/K through ALD and annealing. Emerging materials including GeSn alloys and semiconducting SWCNT networks show promise, with SWCNTs achieving a TCR of −6.5%/K and noise equivalent power (NEP) as low as 1.2 mW/√Hz. Advances in FPA technology feature pixel pitches reduced to 6 μm enabled by vertical nanotube thermal isolation, alongside the 3D heterogeneous integration of single-crystalline Si-based materials with readout circuits, yielding improved fill factors and responsivity. State-of-the-art VO_x-based FPAs demonstrate noise equivalent temperature differences (NETD) below 30 mK and specific detectivity (D*) near 2 × 10¹⁰ cm⋅Hz ^1/2/W. Future advancements will leverage materials-driven innovation (e.g., GeSn/SWCNT composites) and process optimization (e.g., plasma-enhanced ALD) to enable ultra-high-resolution imaging in both civil and military applications. This review underscores the central role of material innovation and system optimization in propelling microbolometer technology toward ultra-high resolution, high sensitivity, high reliability, and broad applicability.

High-resolution short-wave infrared (SWIR) imaging requires photodetectors (PDs) with simultaneously low dark current and high responsivity. To achieve this goal, we demonstrate low-defect bulk germanium-on-insulator (bulk-GeOI) PDs designed for enhanced 1550 nm absorption and suppressed dark current via a resonant cavity and low-defect material platform. Devices were fabricated by direct bonding low-defect bulk Ge and thinning it to ~1300 nm, with an intrinsic layer thickness of only 800 nm. This design avoids epitaxial defects to lower intrinsic dark current while forming a resonant cavity for enhanced responsivity at 1550 nm. Precise doping and Al₂O₃/Si₃N₄ bilayer sidewall passivation were employed. From a design perspective, using low-defect bulk Ge minimizes the defects from epitaxial growth and reduces intrinsic dark current, while thinning the Ge layer enhances the resonant cavity effect to improve 1550 nm responsivity. Experimentally, despite the thin absorbing layer, our devices achieved nA-level dark currents (e.g., 18 nA at −1 V for 10 μm devices) alongside high responsivities. Detailed analysis indicates that this dark current is predominantly attributed to surface and sidewall defects from mesa etching, with minimal contribution from low-defect bulk material defects, validating the effectiveness of the bulk-Ge approach in suppressing intrinsic bulk leakage. Optically, the devices achieved high responsivities of 0.85 A/W (1310 nm) and 0.72 A/W (1550 nm), corresponding to external quantum efficiencies of 80.6% and 57.7%, respectively. This work establishes the bulk-GeOI platform as a promising path toward high-performance SWIR PDs, successfully decoupling high responsivity from bulk leakage and paving the way for future gains through refined surface and interface engineering.

Germanium (Ge) has long been regarded as a promising channel material, owing to its superior carrier mobility and highly tunable electronic band structure. The new generation of low-power electronics is approaching the formation of fully depleted (FD) transistors on Si-on-insulator (SOl) and Ge-on-insulator (GOl) substrates. In this work, we present a full process of a novel FDGOI transistor formed on a strained GOI with low defect density. This scalable and industry-compatible approach enables the formation of uniform 50 nm thick Ge layers by using spinning wet etch with ultrasmooth surfaces (RMS roughness = 0.262 nm) and a low etch-pit density of ~10⁵ cm⁻². Electrical measurements reveal excellent carrier transport properties, with back-gate (BG) transistors achieving mobilities of 550–600 cm²/V·s, while front-gate (FG) devices exhibit sharp switching behavior and steep subthreshold slopes, yielding I_ON/I_OFF ratios up to 10⁵. Temperature-dependent measurements further demonstrate a pronounced enhancement of device performance: the I_ON/I_OFF ratio increases to 106, the subthreshold swing (SS) decreases from 179 mV/dec at room temperature to 137 mV/dec at 120 K, and the threshold-voltage shift with temperature is as low as 1.87 mV/K across the range of 30–300 K. Such behavior highlights the potential of band-gap engineering for precise threshold-voltage control. Taken together, these results establish GOI as a CMOS-compatible material platform and provide a solid technological basis for the development of next-generation low-power transistors beyond conventional CMOS scaling.