The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

We describe a spin logic device with controllable magnetization switching of perpendicularly magnetized ferromagnet/heavy metal structures on a ferroelectric (1- ${x}$ ) [Pb(Mg _1/3 Nb _2/3 )O ₃ ]- x [PbTiO3] (PMN-PT) substrate using current-induced spin-orbit torque. The devices were operated without an external magnetic field and controlled by voltages as low as 10 V applied across the PMN-PT substrate, which is much lower compared with the previous reports (500 V). The deterministic switching with smaller voltage was realized from the virgin state of the PMN-PT. The ferroelectric simulation shows the unsaturated minor loop exhibits obvious asymmetries in the polarizations. Larger polarization can be induced from the initial ferroelectric state, while it is difficult for opposite polarization. The XNOR, AND, NAND, and NOT logic functions were demonstrated by the deterministic magnetization switching from the interaction between the spin-orbit torque and electric field at the PMN-PT/Pt interface. The nonvolatile spin logic scheme in this letter is simple, scalable, and programmable, which are favorable in the logic-in-memory design with low energy consumption.

High performance negative capacitance (NC) p-type FinFETs (p-FinFETs) with a 3-nm-thick ferroelectric (FE) hafnium zirconium oxides (Hf0.5Zr0.5O2) layer are fabricated based on a conventional high-κ metal gate (HKMG) FinFETs fabrication flow. The devices show improved subthreshold swing (SS) values (34.5 mV/dec for 500-nm gate length (LG) and 53 mV/dec for 20-nm-LG devices) and slight hysteresis voltages (~9 mV for LG = 500 nm and ~40 mV for LG = 20 nm transistors). With the integrated FE film, a strong driving current enhancement (up to 260%) is also obtained compared with that of conventional FinFETs. The inherent reasons for the improved characteristics contribute to the low interface state density (Dit) and the perfect channel electrostatic integrity.

In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 10¹⁸ cm⁻³, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger I_ON/I_OFF ratio (3.15 × 10⁵) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

We present a comprehensive theoretical investigation of the quantum confinement limited mobility in the Si1-xGex-channel gate-all-around (GAA) nanosheet field effect transistor (NSFET) for 5 nm node. The study encompasses physics-based quantum mechanical models both for P and NMOS with specified channel/wafer orientations and channel thicknesses, including (1) k.p model with Poisson solver for band structures, bandgap variations, and confined charge distributions, (2) Kubo-Greenwood model for low field mobility with considering surface roughness and stress, (3) Multi-subband Boltzmann transport equation (BTE) based on a state-of-the-art phase space approach is employed to evaluate device IV characteristics, (4) the threshold voltage (VT) variations with different channel/wafer orientations are also evaluated. Our simulation study shows that {110} wafer Ge channel can be an attractive option for 5nm node PMOS, and Si is still promising for NMOS due to strong quantum confinement in Ge channel.