Analog digital video recorders (DVRs) are still extensively used in small-to-medium business and home security systems, but there are special problems when it comes to forensic recovery of video evidence in these systems that are not covered by tools or methodology. Compared to the IP-based network video recorders, analog DVRs packetize video frames of several coaxial-connected cameras into a single interleaved binary stream on disk, necessitating channel demultiplexing before single camera footage can be reassembled. In this paper, we discuss a multi-channel analog Dahua DVR system utilizing the DHAV frame format, with a focus on the forensic recovery approach. Three significant contributions are presented in the methodology: (1) a channel demultiplexing algorithm that separates interleaved frames with up to 32 cameras on the basis of embedded channel identifiers and temporal coherence analysis; (2) a frame sequence stitching mechanism to reassemble continuous video segments on the basis of non-contiguous disk fragments using adaptive frame number tolerance (±3 frames) and temporal validation (≤1 second difference); and (3) a native C implementation with Win32 GUI providing significant performance improvements over interpreted alternatives. The system was tested on 14 analog Dahua DVR hard drives of various models, with a 92.3% recovery rate (97.1% on hard drives with no hardware damage), 91.3% temporal accuracy, 97.5% channel separation accuracy and a 1.8% false positive rate. The methodology fills an important gap in the literature of surveillance forensics, where current studies have only concentrated on IP-based digital systems, and analog DVRs form an estimated 35–40% of operational surveillance systems across emerging markets. The channel demultiplexing capability, which is not found in any current commercial or academic tool, enables automated per-camera organization of interleaved streams, converting what was previously a manual multi-day process into an automated one.

With the increasing prevalence of Internet of Things (IoT) devices in areas like authentication, data protection, and access control, general purpose microcontrollers (MCUs) have become the primary platform for security-critical apps. However, the expense of these attacks has decreased significantly in recent years, making them a viable threat to MCU-based devices. We present a framework-driven perspective with a comparative survey of MCU fault injection resilience for IoT. The survey supports—and is organized around—the procedural evaluation framework we introduce. We discuss the basic requirements for security first, and then categorize the common types of hardware intrusion, including side-channel attacks, fault injection attacks, and invasive methods. We synthesize reported security technologies employed by MCU vendors, such as TrustZone/TEE, Physical Unclonable Functions (PUF), secure boot, flash encryption, secure debugging, and tamper detection, in the context of FIA scenarios. A comparison of representative MCUs—STM32U585, NXP LPC55S69, Nordic nRF54L15, Espressif ESP32-C6, and Renesas RA8M1—highlights cost–security trade-offs relevant to token-class deployments. We position this work as a framework/perspective: an evidence-first FI evaluation protocol for token-class MCUs, a portable checklist unifying PSA/SESIP/CC expectations, and a set of concrete case studies (e.g., ESP32-C6 secure boot hardening). We do not claim a formal systematic review.

This article presents and experimentally validates a formalized development flow for a specialized cryptographic controller designed for hardware implementation of digital signature algorithms. The flow covers the complete design cycle, encompassing architectural synthesis, RTL implementation, FPGA-based hardware verification, and physical implementation within an MPW flow. The controller architecture follows a modular design principle, in which the system is decomposed into functionally independent hardware blocks that are developed and verified individually. For each block, RTL implementation, software interface generation, and hardware verification are carried out during FPGA prototyping, enabling early detection of functional and interface errors. Critical components undergo additional physical verification through an RTLto-GDS flow, including DRC and LVS checks. Upon completion of modular verification, the blocks are integrated, a memory map is generated, and system-level hardware verification is performed. The approach was experimentally validated on a demonstration computing module based on the TinyQV (RISC-V) core, using the GOWIN Tang Primer 20K and TinyTapeout (PDK SkyWater SKY130) platforms. The results confirm the reproducibility of the proposed flow and its practical applicability for developing specialized cryptographic controllers and secure embedded systems.

This article proposes and experimentally validates a formalized development flow for a specialized cryptographic controller designed for hardware implementation of electronic digital signatures. The proposed flow is a methodology encompassing the full development cycle – from architectural design to project preparation for MPW production. The controller architecture is based on a modular principle, whereby the system consists of functionally independent hardware blocks developed and verified as individual modules. Each module undergoes RTL implementation, hardware abstraction layer development, and hardware verification during FPGA prototyping. Critical modules are subjected to hardware verification and physical validation within the MPW pipeline. Following modular verification, the blocks are integrated into the system, the final memory map is generated, and system hardware verification is conducted. Experimental validation of the methodology was carried out on a TinyQV demonstration computing module compatible with the RISC-V architecture. Hardware verification was executed on the GOWIN Tang Primer 20K FPGA platform, and the physical implementation was realized in the TinyTapeout platform MPW flow using the SkyWater SKY130 PDK. The results confirm the reproducibility of the proposed development path and its applicability for creating specialized cryptocontrollers for information security and embedded systems.

The article explores modern integrated circuit production methods with the aim of creating a crypto controller in the Republic of Kazakhstan. The paper analyzes global trends in the semiconductor industry, technological features and economic aspects of integrated circuit production, and also identifies directions for the development of the semiconductor industry in Kazakhstan for the development of security hardware. The research methodology includes an analysis of modern integrated circuit design and manufacturing methods, based on a comparison of various technological processes, plans, and projects implemented in countries with mature, intermediate, and leading-edge integration and productivity capabilities. Research results show that for the Republic of Kazakhstan, which lacks its own integrated circuit production base, the optimal approach is to develop a fabless model with design within the country and production at third-party foundries. This doesn't require significant investment compared to building national production capacity in mature nodes. The paper proposes a phased approach to creating a domestic crypto controller, starting with prototyping on programmable logic and subsequently transferring the architecture to a specialized integrated circuit. The practical value of the work lies in the identification of optimal opportunities for organizing the production of semiconductor microchips in Kazakhstan and developing a domestic crypto controller at a level ready for industrial production.