This paper presents a capacitor voltage balancing control applicable to any multilevel dc-ac converter formed by a single set of series-connected capacitors implementing the dc link and semiconductor devices, such as the diode-clamped topology. The control is defined for any number of dc-link voltage levels and converter legs (for single-phase and multiphase systems), guaranteeing the capacitor voltage control for any modulation index value and load (from idle mode to full power). The associated control loop small-signal transfer function is presented, from which optimum compensator design guidelines are derived. The improvement in control performance is verified through simulation and experiments comparing with a previous balancing control strategy in a four-level three-phase dc-ac conversion system. The satisfactory control performance is also verified through simulation in a four-level five-phase dc-ac conversion system.

With the aim to implement a suitable controller for a three-phase dc-ac multilevel active-clamped converter to enable its use in practice, and as a first step toward a full closed-loop converter control implementation into a single field-programmable gate array (FPGA) device, this paper presents the structure and features of an FPGA implementation of an appropriate pulsewidth modulation (PWM) strategy. The selected PWM strategy guarantees dc-link capacitor voltage balance in every switching cycle, and covers both the undermodulation and overmodulation regions. A flexible implementation is conceived, allowing the variation of important operating parameters, such as the modulation index and switching frequency, through a simple user interface. The key aspects to achieve an efficient and robust FPGA implementation are discussed. Experimental results in a four-level converter prototype controlled with an Altera Cyclone III device under different operating conditions match fairly well with the expected results obtained through simulation, thus verifying the accurate performance of the FPGA-based modulator.

Microprobing is commonly used by adversaries to extract firmware or cryptographic keys from microcontrollers. We introduce the calibratable lightweight invasive attack detector (CaLIAD) to detect microprobing attacks. The CaLIAD measures timing imbalances between lines that are caused by the capacitive load of a probe. Compared to protection mechanisms from industry, it does not require an additional protection layer such as meshes do; in contrast to bus encryption, it does not introduce delay cycles. Compared to state-of-the-art low area probing detectors, it can be calibrated and, thus, allows compensating manufacturing variations as well as small layout imbalances. This capability allows us to significantly reduce the detection margin compared to the prior art while maintaining the low rate of false positives. We can finally show that capacitive loads of 23 fF or less can be detected, depending on how the CaLIAD is used. This includes all state-of-the-art commercial microprobes we are aware of.

In this paper, a low-cost method to verify functional specifications of analog VLSI circuits is proposed. The method is based on the analysis of Lissajous signatures combined with regression techniques. In order to obtain Lissajous signatures, the observation space is partitioned into zones using hyperplanes, and a set of integer values used as the digital signature of the circuit is generated by Lissajous curve zone crossings. A predictor function obtained by nonlinear regression techniques predicts the functional specification parameters of the circuit under consideration. The viability of this methodology is analyzed and applied to verify the center frequency f ₀ of a bandpass biquad filter. Experimental measurements show an accurate prediction of the center frequency of the designed filter.

This paper proposes a closed-loop control implementation fully-embedded into an FPGA for a permanent-magnet synchronous motor (PMSM) drive based on a four-level active-clamped converter. The proposed FPGA controller comprises a field-oriented control to drive the PMSM, a DC-link voltage balancing closed-loop control (VBC), and a virtual-vector-based modulator for a four-level active-clamped converter. The VBC and the modulator operate in consonance to preserve the DC-link capacitor voltages balanced. The FPGA design methodology is carefully described and the main aspects to achieve an optimal FPGA implementation using low resources are discussed. Experimental results under different operating conditions are presented to demonstrate the good performance and the feasibility of the proposed controller for motor-drive applications.

A compact built-in current sensor based on a slightly modified latch comparator is presented, which allows fast detection and memorising of excessively high quiescent current without the need for a voltage reference. Response time, virtual ground distortion and silicon overhead are analysed in order to evaluate the sensor performance.