This paper proposes a novel device designated as an intelligent electronic fuse (iFuse) intended to be connected in series with any current-bidirectional voltage-unidirectional active switch present in a power converter. The iFuse duty is to selectively isolate its series-associated switch from the rest of the converter circuit immediately after detecting that this switch has failed in short circuit. Nonetheless, it maintains the reverse (free-wheeling) current path originally offered by the failed switch. The failure detection is typically performed when the failed switch causes a shoot-through event. Therefore, the iFuse is able to block large currents. The iFuse allows increasing the power-converter fault tolerance and reliability with regard to switch short-circuit failures, as in converters featuring switches in parallel, redundant legs, and multilevel neutral-point-clamped topologies. The reliability model analysis of a two-level converter leg with two parallel switches per position, reveals that its reliability can be increased up to four times when an iFuse is implemented in series with each switch. The iFuse device feasibility and good performance is verified through experimental tests, proving that it can detect and isolate the associated-switch failure in 6 μs, while stopping short-circuit currents of up to 1 kA without incurring in harmful di/dt values.

The battery is at the heart of the electric vehicle and determines many of its key performance features. Therefore, an optimized design of the battery is critical. On one hand, the design of batteries based on a single battery cell leads in many cases to oversized batteries in terms of energy or power, due to the diversity of requirements of the different electric vehicles. On the other hand, the use of a custom cell for each vehicle, optimized for its particular requirements, is not economically viable. Instead, hybrid batteries, combining only two battery cell chemistries, with distinct particular strengths, such as high specific energy or high specific power, offer an opportunity to cover a wide range of vehicle battery specifications while avoiding oversizing and a dispersion in the cells to be employed. This work introduces a novel hybrid battery configuration, where the interfacing between the two sets of cells is accomplished through a bidirectional multilevel neutral-point-clamped dc-dc converter. The novel topology is presented and a suitable power converter modulation and control strategy is developed. The feasibility and benefits of such configuration are demonstrated and illustrated. Particularly, the proposed battery system allows the balancing of the state-of-charge (SoC) of the battery modules within both sets of battery banks, which is achieved without introducing additional power losses. The SoC balancing is simply accomplished through the regulation of the power to be extracted/delivered from/to each battery module by the power converter during regular battery discharging and charging operations. The converter features enough regulation margin to correct substantial SoC imbalances. Overall, the proposed approach enables a modular and scalable design of the energy storage system for a wide range of electric vehicles, from only two different standard battery modules and a standard power semiconductor device, while optimizing the battery size for any given battery power and energy specification. Simulation and experimental results are provided in the case of a three-level internal battery interfacing to verify the good performance of the proposed novel hybrid battery configuration, modulation, and control.

Nowadays, the internal combustion engine in vehicles is being replaced by electric motors, giving way to the electric vehicle, which results in reduced environmental impact, higher efficiency and lower emission of greenhouse gases. The powertrain of an electric vehicle is its most prominent subsystem, with the batteries and traction inverter being key components. Thus, due to their relevance, advances in the design of both components are of paramount importance. In this paper, the potential benefits achieved through a powertrain design approach based on combining a modular battery bank with multilevel NPC traction inverter topologies were analyzed, in comparison to a conventional two-level powertrain design. Several aspects were analyzed: modularity, complexity, battery-pack state-of-charge balancing, inverter loss, motor ac voltage harmonic distortion, motor common-mode voltage and reliability. Particularly, from the comparison study developed under the selected design scenario, the proposed design approach, based on modular battery packs and multilevel technology, shows a potential reduction of up to 55% in inverter losses, up to 65% in motor ac-voltage total harmonic distortion, and up to 75% in rms common-mode voltage.

This paper proposes a closed-loop control implementation fully-embedded into an FPGA for a permanent-magnet synchronous motor (PMSM) drive based on a four-level active-clamped converter. The proposed FPGA controller comprises a field-oriented control to drive the PMSM, a DC-link voltage balancing closed-loop control (VBC), and a virtual-vector-based modulator for a four-level active-clamped converter. The VBC and the modulator operate in consonance to preserve the DC-link capacitor voltages balanced. The FPGA design methodology is carefully described and the main aspects to achieve an optimal FPGA implementation using low resources are discussed. Experimental results under different operating conditions are presented to demonstrate the good performance and the feasibility of the proposed controller for motor-drive applications.

Conventional configurations for neutral-point-clamped multilevel converters exhibit an uneven power loss distribution among their power semiconductor devices. In particular, this imbalance increases the temperature of power semiconductor devices situated at specific locations within the converter layout, thereby reducing the reliability of the system. To mitigate this issue, neutral-point-clamped multilevel converters can be implemented using a switching-cell array design. This design allows for multiple topology configurations and inherently introduces redundant conduction paths, thus reducing conduction losses and also providing greater flexibility in distributing the switching losses. This work analyzes the thermal behavior of various configurations of a four-level dc–ac neutral-point-clamped converter based on a switching-cell array. An active thermal control strategy is used to distribute the switching losses, in order achieve a more uniform temperature distribution across the converter. Experimental results confirm that, compared to conventional neutral-point-clamped converter implementations, configurations based on a switching-cell array combined with active thermal control achieve a more uniform distribution of power losses. This leads to significantly improved temperature uniformity across the converter, thereby reducing thermal stress and enhancing overall system reliability.

This study presents a comprehensive analysis of three bipolar-junction-transistor (BJT) amplifier topologies common-emitter, common-collector, and common-base amplifiers-under transient conditions across low and high frequencies. Utilizing MATLAB-Simulink simulations, the response of each amplifier topology to varying frequency inputs is investigated, with a particular emphasis on state space modeling. Beginning with low-frequency models characterized by specific voltage or current sources, the study delves into the steady-state dynamics of output variables, employing state space equations to elucidate amplifier behavior. Notably, the common-emitter amplifier topology exhibits high gains, as corroborated by established literature, underlining its potential for high-performance applications. Conversely, the common-collector and common-base amplifier topologies demonstrate lower gains, reflecting distinct design characteristics. Transitioning to high-frequency operation, the impact of Miller capacitance on gain reduction is explored, especially pronounced in the common-emitter amplifier topology. Despite this, all amplifier configurations remain functional, with state space models validated through meticulous simulations. Simulation parameters are meticulously adjusted to accurately represent real-world scenarios, enhancing the reliability of the findings. These insights underscore the importance of comprehending amplifier behavior across different frequency domains, with state space modeling offering a powerful framework for analysis. By providing detailed insights into BJT amplifier performance under transient conditions, this study facilitates informed decisions regarding amplifier configuration selection and design, tailored to specific application requirements and frequency considerations.