Loukas Chevas

Mr. Loukas Chevas

orcid

Research Focus & Metrics

Academic Career Length

7Years (2020-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

View All Publications
7 September 2020 in IEEE Transactions on Electron Devices
Verified
Journal Article
Closed access
MBMatthias Bucher
Matthias Bucher
NMNikolaos Makris
Nikolaos Makris
LCLoukas Chevas
Loukas Chevas
A novel method for extracting threshold voltage and substrate effect parameters of MOSFETs with constant current bias at all levels of inversion is presented. This generalized constant-current (GCC) method exploits the charge-based model of MOSFETs to extract threshold voltage and other substrate-effect-related parameters. The method is applicable over a wide range of current throughout weak and moderate inversion, and to some extent in strong inversion. This method is particularly useful when applied for MOSFETs presenting edge conduction effect (subthreshold hump) in CMOS processes using shallow trench isolation (STI).

6 October 2020 in IEEE Transactions on Electron Devices
Verified
Journal Article
Closed access
NMNikolaos Makris
Nikolaos Makris
MBMatthias Bucher
Matthias Bucher
LCLoukas Chevas
Loukas Chevas
FJFarzan Jazaeri
Farzan Jazaeri
JSJean-Michel Sallese
Jean-Michel Sallese

31 December 2025 in Fluctuation and Noise Letters
Verified
Journal Article
Closed access
RCRaphael Chatzipantelis
Raphael Chatzipantelis
LCLoukas Chevas
Loukas Chevas
NMNikolaos Makris
Nikolaos Makris
MBMatthias Bucher
Matthias Bucher

3 July 2026 in Instruments
Verified
Journal Article
Open access
PDF file
LCLoukas Chevas
Loukas Chevas
MBMatthias Bucher
Matthias Bucher
NMNikolaos Makris
Nikolaos Makris
IFIoannis S. Fosteris
Ioannis S. Fosteris
NFNikolaos Fasarakis
Nikolaos Fasarakis
GKGeorge Konstantinidis
George Konstantinidis
The bias-dependent capacitance of varactors can introduce harmonic distortion into the circuits where they are utilized. A gate capacitance model valid through inversion–depletion has been presented for GaN HEMT varactors in the drive for their utilization in monolithic GaN ASICs. This work focuses on the circuit and the methodology employed to accurately measure on wafer the harmonic distortion caused by one such device. The circuit is presented and its design considerations and operation trade-offs are discussed, followed by a presentation of the measurements resulting from its use. Second- and third-order harmonic distortion is recorded and presented, with Verilog-A model simulations used to fit the measured data. The model consists of a charge-based expression of the HEMT varactor capacitance, with a minimal number of parameters. The good fit of the model is demonstrated, proving both the suitability of the circuit used for the measurements and the validity of the capacitance model for real-world applications.