Interconnect resistance and reliability have emerged as critical factors limiting the performance of advanced CMOS circuits. With the slowdown of transistor scaling, interconnect scaling has become the primary driver of continued circuit miniaturization. The associated scaling challenges for interconnects are expected to further intensify in future CMOS technology nodes. As interconnect dimensions approach the 10 nm scale, the limitations of conventional Cu dual-damascene metallization are becoming increasingly difficult to overcome, spurring over a decade of focused research into alternative metallization schemes. The selection of alternative metals is a highly complex process, requiring consideration of multiple criteria, including resistivity at reduced dimensions, reliability, thermal performance, process technology readiness, and sustainability. This Tutorial introduces the fundamental criteria for benchmarking and selecting alternative metals and reviews the current state of the art in this field. It covers materials nearing adoption in high-volume manufacturing, materials currently under active research, and potential future directions for fundamental study. While early alternatives to Cu metallization have recently been introduced in commercial CMOS devices, the search for the optimal interconnect metal remains ongoing.

We report on scaled finFETs built with a novel routing scheme wherein devices are connected via buried power rails (BPRs) from both wafer sides, with tight variability and matching control. On the wafer’s frontside (FS), M1 lines (FSM1) are connected through V0 vias to M0A lines which are then linked to BPR lines by vias called VBPR while also contacting directly the device’s S/D-epi. As for gate wiring, to enable in this work its access from both wafer sides, gate is also connected to BPR via V0 landing on it and on a neighboring M0A line set only on field-oxide. A single-step metallization for M0A and VBPR is preceded by in situ preclean(s) optimized for improved BPR-VBPR contact interface and $\textit{R}_{\text{ext}}$ , as confirmed electrically and by physical analysis. After FS processing, wafer flipping, bonding, and extreme thinning, highly scaled, $\sim $ 323 nm deep nano-through-Si-vias (nTSVs) land on BPR, with tight overlay control and unchanged BPR resistance 26%–29% lower with improved tungsten (W)-fill, connecting them to the first backside (BS) metal level (BSM1). By moving the power delivery network to the BS (BSPDN), besides alleviating FS routing congestion, considerably smaller dynamic and static IR drop values are predicted from on-chip power heat maps generated for a low power 64-bit CPU at 2-nm design rules: 82% and 96% less worst-case values versus a reference configuration, respectively. P/NMOS show similar or even superior $\textit{I}_{\biosc{on}}$ – $\textit{I}_{\biosc{off}}$ after BS processing and extra anneal(s) added for $\textit{V}_{\textit{T}}$ recovery, mobility and bias temperature instability (BTI) improvement—up to 8%/15% higher $\textit{I}_{\biosc{on}}$ linked to anneal selection.

CuxAl1−x thin films with 0.2 ≤ x ≤ 0.7 have been studied as potential alternatives for metallization of advanced interconnects. First-principles simulations were used to obtain the CuxAl1−x electronic structure and cohesive energy to benchmark different intermetallics and their prospects for interconnect metallization. Next, thin CuxAl1−x films were deposited by PVD with thicknesses in the range between 3 and 28 nm. The lowest resistivities of 9.5 μΩ cm were obtained for 28 nm thick stoichiometric CuAl and CuAl2 after 400 °C postdeposition annealing. Based on the experimental results, we discuss the main challenges for the studied aluminides from an interconnect point of view, namely, control of the film stoichiometry, the phase separation observed for off-stoichiometric CuAl and CuAl2, as well as the presence of a nonstoichiometric surface oxide.

We studied the metal gate work function of different metal electrode and high-k dielectric combinations by monitoring the flat band voltage shift with dielectric thicknesses using capacitance–voltage measurements. We investigated the impact of different thermal treatments on the work function and linked any shift in the work function, leading to an effective work function, to the dipole formation at the metal/high-k and/or high-k/SiO₂ interface. We corroborated the findings with the erase performance of metal/high-k/ONO/Si (MHONOS) capacitors that are identical to the gate stack in three-dimensional (3D) NAND flash. We demonstrate that though the work function extraction is convoluted by the dipole formation, the erase performance is not significantly affected by it.