Digital Peak Current Mode (DPCM) control is widely used for DC-DC converters operating in Continuous Current Mode (CCM). However, Current Tracking Delay (CTD) in the system is normally neglected in the modelling stage, which leads to poor compensator design and degraded performance. This paper investigates CTD effect in boost converter with different DPCM controls. Based on dynamic relationship between the reference current and actual inductor current, the CTD transfer functions are derived, which improves the accuracy of Small Signal Model (SSM). Since CTD degrades the phase margin of the system, equivalent migration of Right Half Plane (RHP) zero is proposed to model CTD effect. This method is very simple and straightforward, which facilitates the compensator design. Furthermore, two novel DPCM control strategies with minimized CTD are proposed, and they are based on duty cycle restriction and duty cycle extension, respectively. Both controls greatly reduce the CTD effect and improve the response speed. Besides, the duty cycle extension benefits from an Extended Pulse Width Modulation (ExPWM). This optimizes the calculation algorithm and speed, while improves the time margin for digital calculations. Combined with the proposed models and controls, the CTD effect is greatly reduced. The effectiveness is verified through detailed simulations and experiments.

As the demands of big data applications and deep learning continue to rise, the industry is increasingly looking to artificial intelligence (AI) accelerators. Analog in‐memory computing (AiMC) with emerging nonvolatile devices enable good hardware solutions, due to its high energy efficiency in accelerating the multiply‐and‐accumulation (MAC) operation. Herein, an Applied Materials custom‐designed system‐on‐chip (SoC) targeting AI applications with analog in‐memory computing using resistive random‐access memory (ReRAM) as the compute element is demonstrated. The first silicon achieves high energy efficiency in MAC operations. This chip is implemented with LeNet‐1 neural network on ReRAM tiles and demonstrated by Modified National Institute of Standards and Technology (MNIST) classification with accuracy matching that predicted in the simulations. A simulation framework, AI Sim, is also developed to evaluate the system performance for large‐scale application and guide the bitcell development and design choices.

The mathematical models of five-phase permanent magnet synchronous motor (PMSM) in abc frame and alphabeta frame are established, and the relationships between the torque and fundamental components, loss and harmonic components are revealed. To suppress the high third harmonic current appeared in five-phase machine especially, a novel space vector pulse width modulation (SVPWM) method which has a feature of low harmonic is proposed. The proposed method is adopted to implement the direct torque control (DTC) of a five-phase PMSM, and a good torque and current performance are got and validated by simulation and experiment.

This paper presents an Optimized Sensorless Charge Balance (OSCB) controller based on a damped current model for flyback converter operating in Discontinuous Conduction Mode (DCM). By solving total differential equations of non-ideal transformer currents, the damped current model is derived with consideration of parasitics, leakage inductance of transformer, and the Resistor-Capacitor-Diode (RCD) snubber circuit. Based on the proposed model, current observation and control algorithms of the Sensorless Charge Balance (SCB) controller are optimized, which forms the OSCB control strategy. The average current damping is considered in the equivalent discrete-time small signal model. Furthermore, frequency analyses show that OSCB controller achieves higher closed-loop bandwidth and lower overshoot than a SCB controller, which indicates an improved transient performance. Finally, both OSCB and conventional SCB controllers are experimentally evaluated on a flyback converter prototype.