A contact resistance ( ${R}_{c}$ ) becomes a major parasitic resistance in highly scaled modern semiconductor devices. A wrap-around contact (WAC) has been suggested as a promising solution to reduce the ${R}_{c}$ , because its contact area is larger than that for the conventional top contact (TC) structure. Therefore, in this article, the electrical and thermal characteristics are widely investigated in vertically stacked gate-all-around (GAA) MOSFET with a WAC by using a 3-D technology computer-aided design (TCAD) simulation. First, compared with the TC, the WAC shows 1.74 times higher ON-state current. It is attributed in part to the low ${R}_{c}$ and in part to the low source–drain resistance ( ${R}_{\text {SD}}$ ). Furthermore, thermal resistance ( ${R}_{\text {th}}$ ) is also reduced by 9.73% in WAC, which improves self-heating effects (SHEs). Considering the results, it is expected that the WAC structure could be an attractive candidate to simultaneously improve device performance and reliability.

For improving self-heating effects (SHEs) in gate-all-around metal-oxide-semiconductor field-effect transistors (GAA MOSFETs), hetero-gate-dielectric (HGD) is utilized. The HGD consists of hafnium dioxide (HfO2) and silicon dioxide (SiO2), which has high thermal conductivity, hence SHEs are improved. In order to validate the HGD, technology computer-aided design (TCAD) simulation is performed through Synopsys Sentaurus three-dimensional (3D) tool. As a result, when the HGD is adopted in GAA MOSFETs, SHEs can be significantly improved from 498 K to 415 K. In addition, suppression of gate current, more than 2 orders, is also achieved because of bigger bandgap of SiO2 in HGD. Consequently, this structure takes advantage of higher thermal conductivity and bigger bandgap of SiO2, and higher permittivity of HfO2 for improving SHEs and gate leakage current.

By utilizing the dual- $\kappa $ spacer (DS) technique, a novel structure has been proposed to improve the thermal characteristics and ON-current ( I $_{\biosc{on}}\text{)}$ in gate-all-around (GAA) MOSFETs. The proposed GAA MOSFET structure utilizes DS, which contains aluminum oxide (Al $_{\text{2}}$ O $_{\text{3}}\text{)}$ as an inner spacer so that the self-heating effect (SHE) could be improved from the high thermal conductivity of Al $_{\text{2}}$ O $_{\text{3}}$ . To verify the proposed device structure, 3-D technology computer-aided design (TCAD) simulation has been performed through Synopsys Sentaurus tool. As a result, when the DS structure and Al $_{\text{2}}$ O $_{\text{3}}$ are utilized in GAA MOSFET, the maximum lattice temperature ( $\textit{T}_{\text{max}}\text{)}$ is improved from 628 to 509 K, and the thermal resistance ( $\textit{R}_{\text{th}}\text{)}$ is improved by 49%. According to this thermal improvement, I $_{\biosc{on}}$ and OFF-current ( I $_{\biosc{off}}\text{)}$ are also simultaneously improved in the proposed GAA MOSFET. Furthermore, since Al $_{\text{2}}$ O $_{\text{3}}$ has lower permittivity than HfO $_{\text{2}}$ , the gate capacitance ( $\textit{C}_{\text{gate}}\text{)}$ could also be improved in the proposed GAA MOSFET. In essence, the proposed GAA MOSFET structure utilizes high thermal conductivity and low permittivity of Al $_{\text{2}}$ O $_{\text{3}}$ with DS structure.

For the first time, a comprehensive study is done regarding the stability under simultaneous application of light and gate dc bias in amorphous hafnium-indium-zinc-oxide (α-HIZO) thin-film transistors (TFTs). Subthreshold swing (SS) degradation, a negative threshold voltage (V_th) shift, and the occurrence of hump are observed in transfer curves after applying a negative gate bias and light stress. Based on the retention test at room temperature and the hysteresis analysis, it is revealed that all these phenomena result from hole trapping in the gate insulator. Moreover, it is proven that the SS degradation and hump occurrence are mainly attributed to hole trapping in SiO₂ at the edge regions along the channel length/width directions and that a negative V_th shift is derived from hole trapping in the gate insulator far from the SiO₂/HIZO interface.

In this report, a novel tunnel field-effect transistor (TFET) named ‘F-shaped TFET’ has been proposed and its electrical characteristics are analyzed and optimized by using a computer-aided design simulation. It features ultra-thin and a highly doped source surrounded by lightly doped regions. As a result, it is compared to an L-shaped TFET, which is a motivation of this work, the F-shaped TFET can lower turn-on voltage (V_ON) maintaining high on-state current (I_ON) and low subthreshold swing (SS) with the help of electric field crowding effects. The optimized F-shaped TFET shows 0.4 V lower V_ON than the L-shaped TFET with the same design parameter. In addition, it shows 4.8 times higher I_ON and 7 mV/dec smaller average SS with the same V_ON as that for L-shaped TFET.

The main challenge for tunnel field-effect transistors (TFETs) is achieving high on-current (Ion) and low subthreshold swing (SS) with reasonable ambipolar characteristics. In order to address these challenges, Ge-channel heterostructure TFET with Si source and drain region is proposed, and its electrical characteristics are compared to other TFET structures. From two-dimensional (2-D) device simulation results, it is confirmed that the Si/Ge heterostructure source junction improves Ion and SS characteristics by using the direct band-to-band tunneling current. Furthermore, the proposed structure shows suppressed ambipolar behavior since the Ge/Si heterostructure is used at the drain junction.