This paper examines a tunnel field-effect transistor (TFET) as a promising device for achieving steeper switching and better electrical performances in low-power operation. It features a double-gate TFET with vertical channel sandwiched by lightly doped Si (VS-TFET). The vertical tunnel junction is employed on the source side for the steeper subthreshold swing (SS) and for the higher on-current (Ion) by restricting tunnel barrier width. The VS-TFET shows 17-mV/dec minimum SS and 10⁴ on/ off current ratio (Ion/Ioff) for sub-0.7-V gate overdrive. In addition, the VS-TFET shows sub-60-mV/dec SS in a wide range of ID regardless of sweep directions. In conclusion, the work presented here demonstrates that the VS-TFET will be one of the most promising candidates for a next-generation low-power device.

We demonstrate a nonvolatile single transistor ferroelectric gate memory device with ultra-thin (5.5 nm) Hf_0.8Zr_0.2O₂ (HZO) fabricated using a self-aligned gate last process. The FETs are fabricated using silicon-on-insulator wafers, and the ferroelectric is deposited with atomic layer deposition. The reported devices have an ON/OFF drain current ratio of up to 10⁶, a read endurance of > 10¹⁰ read cycles, and a program/erase endurance of 10⁷ cycles. Furthermore, healing of the transistor after gate insulator breakdown is demonstrated.

In this brief, several issues attributed to the channel-release process in vertically stacked-gate-all-around MOSFETs (GAAFETs) having various nanosheet (NS) widths were rigorously investigated. Because of the finite selectivity of SiGe (sacrificial layer) etchant to Si (channel layer), Si channel is likely to be thinned during the channel-release step which is one of the key processes in stacked-GAA FET fabrication. Consequently, the thickness of channel and the interchannel space becomes variable depending on the NS width, since the etch time must be determined by the widest channel within a wafer. It results in a channel width dependence of gate work function, gate-to-drain capacitance, and channel interfacial property as well as the electrostatic gate controllability. The electrical characteristic behavior of stacked-GAAFETs induced by these effects was thoroughly investigated through process-based 3-D technology computer-aided design (TCAD) device simulation along with a transmission electron microscopy (TEM) and an energy-dispersive spectroscopy (EDS) analyses. The results confirm that width-dependent effects should be taken into account when fabricating and compact modeling the stacked-GAAFETs with various NS widths which are required for logic and static random access memory (SRAM) applications.

A contact resistance ( ${R}_{c}$ ) becomes a major parasitic resistance in highly scaled modern semiconductor devices. A wrap-around contact (WAC) has been suggested as a promising solution to reduce the ${R}_{c}$ , because its contact area is larger than that for the conventional top contact (TC) structure. Therefore, in this article, the electrical and thermal characteristics are widely investigated in vertically stacked gate-all-around (GAA) MOSFET with a WAC by using a 3-D technology computer-aided design (TCAD) simulation. First, compared with the TC, the WAC shows 1.74 times higher ON-state current. It is attributed in part to the low ${R}_{c}$ and in part to the low source–drain resistance ( ${R}_{\text {SD}}$ ). Furthermore, thermal resistance ( ${R}_{\text {th}}$ ) is also reduced by 9.73% in WAC, which improves self-heating effects (SHEs). Considering the results, it is expected that the WAC structure could be an attractive candidate to simultaneously improve device performance and reliability.