Neuromorphic computing offers parallel data processing and low energy consumption and can be useful to replace conventional von Neumann computing. Memristors are two-terminal devices with varying conductance that can be used as synaptic arrays in hardware-based neuromorphic devices. In this research, we extensively investigate the analog symmetric multi-level switching characteristics of zinc tin oxide (ZTO)-based memristor devices for neuromorphic systems. A ZTO semiconductor layer is introduced between a complementary metal-oxide-semiconductor (CMOS) compatible Ni top electrode and a highly doped poly-Si bottom electrode. A variety of bio-realistic synaptic features are demonstrated, including long-term potentiation (LTP), long-term depression (LTD), and spike timing-dependent plasticity (STDP). The Ni/ZTO/Si device in which the adjustment of the number of states in conductance is realized by applying different pulse schemes is highly suitable for hardware-based neuromorphic applications. We evaluate the pattern recognition accuracy by implementing a system-level neural network simulation with ZTO-based memristor synapses. The density of states (DOS) and charge density plots reveal that oxygen vacancies in ZTO assist in generating resistive switching in the Ni/ZTO/Si device. The proposed ZTO-based memristor composed of metal-insulator-semiconductor (MIS) structure is expected to contribute to future neuromorphic applications through further studies.

This letter examined the natural local self-boosting effect of an inhibited channel in three-dimensional (3D) NAND flash memory. The inhibited channel in the 3D NAND flash structure can be in the floating state easily, because its channel is not connected directly to its substrate. Despite the application of the global self-boosted program-inhibit scheme, the selected wordline cell is localized automatically during the program pulse application. This phenomenon is analyzed using a computer-aided design simulation, and an analytical model of boosted potential of an inhibited channel in 3D NAND flash memory is proposed.

This paper proposes a synaptic device based on charge-trap flash memory that has good CMOS compatibility and superior reliability characteristics compared with other synaptic devices. Using hot-electron injection and hot-hole injection, we designed operation methods to implement gradual conductance modulation and spike-timing-dependent plasticity. We demonstrate the feasibility of the device for neuromorphic applications through both a device-level technology computer-aided design simulation and a system-level MATLAB simulation. For the first time, we also propose a 3-D stacked synapse array and present the structure, operation, and process methods. The proposed array architecture features a small area and low process cost and could be a novel solution for neuromorphic systems for implementing deep neural networks.

Various memory devices have been proposed for implementing synapse devices in neuromorphic systems. In this paper, an AND flash array based on charge trap flash (CTF) memory was proposed. CTF-based synapse devices are particularly suitable for off-chip learning applications because they have excellent reliability and stable multi-level operation characteristics. In addition, we proposed a method to implement convolutional neural networks in the proposed array, and performed system-level simulation using the characteristics of the fabricated device. Finally, we investigated the accuracy degradation of the neuromorphic system related to data retention and proposed a multiple cell mapping scheme to address this degradation issue.

The use of nonvolatile arbitrary logic functions through emerging nonvolatile memory devices has been proposed to implement in-memory computing architecture. Here, in this paper, for the first time, we have proposed a nonvolatile stateful logic methodology based on a charge trap flash (CTF) memory device. Using multi-bit operation, functionally complete Boolean logic functions are experimentally demonstrated. The CTF devices exhibit perfect CMOS compatibility and excellent reliability as compared to other emerging memory devices. In addition, they do not require an additional select transistor, which leads to a more compact array configuration. Our CTF device and operation method may be a promising solution for the hardware implementation of non-von Neumann computing systems.

This paper proposes a 3-D floating-gate (FG) synapse array for neuromorphic applications. The designed device has certain advantages over previous planar FG synapse devices: a smaller cell size due to the stacked structure and smaller operation voltage by the gate-all-around geometry. In addition, the operation method to implement spike time-dependent plasticity is proposed and demonstrated. The proposed array based on commercialized flash memory technology is expected be one of the most promising candidate architecture for neuromorphic applications.