Cascaded H-bridge (CHB) multilevel converters are promising candidates for large-scale grid-connected photovoltaic systems (megawatt to gigawatt). However, the conventional CHB multilevel converter cannot ensure the inter-module and inter-phase power balance, resulting in imbalanced grid currents. Therefore, in this paper, a new topology consisting of CHB multilevel converters and interleaved-boost full-bridge LLC (IB-FBLLC)-based three-port dc-dc isolation converters is proposed. In this proposed topology, a common dc bus made up of the low-voltage-side ports of IB-FBLLC-based three-port dc-dc converters can completely solve the inherent power imbalance issues. Moreover, the design parameters of dc-dc converters considering the minimization of the input current ripple and optimization of switching frequency range are discussed in detail. Simulation results of the three-phase system and experimental results of the single-phase system clearly verify the effectiveness and feasibility of the proposed topology and control strategies.

In silicon carbide (SiC) device based motor drives, the high-voltage slew-rate ( dv / dt ) associated with the fast-switching transitions results in excessive motor overvoltage, due to the reflected wave phenomenon, which increases the motor winding insulation stress and causes premature failure while raising electromagnetic interference (EMI) problems. This article proposes a soft-switching voltage slew-rate profiling approach to mitigate the motor overvoltage in SiC-based cable-fed drives. The proposed approach optimizes the rise/fall time of the output voltage according to the cable length, without altering the switching speed of the SiC devices. Since increasing the switching rise/fall time using conventional approaches, such as increasing the gate resistance, results in an increased switching power loss, the proposed profiling approach is implemented using a soft-switching inverter. The optimum rise/fall time that can significantly mitigate the overvoltage is derived using frequency- and time-domain analysis. The auxiliary resonant commutated pole inverter (ARCPI) is adopted as an example of the soft-switching inverter to experimentally verify the proposed slew-rate profiling approach for the overvoltage mitigation. The analysis and experimental results show that the motor overvoltage is fully mitigated when the output voltage rise/fall time is set as the cable antiresonance period, i.e., four times of the wave transmission time along the cable. Furthermore, the slew-rate profiling approach along with the ARCPI reduces the switching loss and improves the EMI performance at the high-frequency region, compared with the conventional hard-switching converter. Specifically, the maximum efficiency of the ARCPI is about 99%.

Efficiency, power quality and reliability of SiC MOSFET-based voltage-source converters are significantly affected by the dead-time settings. The conventional fixed dead-time setting can induce large output voltage loss and additional energy loss due to the output capacitance of the SiC MOSFETs and the SiC SBDs or the freewheeling of the diodes, which will be more serious under high switching frequencies. This paper analyzes and models the detailed switching process of the SiC MOSFET half-bridge circuit when various dead-time settings are adopted. Based on the models, an optimal asymmetric variable dead-time (OAVDT) setting is proposed, which can avoid the discharging loss of the output capacitance and redundant freewheeling loss of the diode. The OAVDT setting is realized by adjusting the optimal dead-time in real time after the active device is turned off, which does not require any additional hardware circuits. The OAVDT setting can also reduce the output voltage loss to a certain level compared to the fixed dead-time setting. A three-phase two-level SiC MOSFET inverter has been built in the lab to verify the proposed OAVDT setting. Experimental results show a decrease of power loss by 22.5% with reduced output voltage loss compared to the fixed dead-time setting of 0.28μs when the output power is 8kW and the switching frequency is 40kHz. The proposed OAVDT setting shows clear advantages over the fixed dead-time setting, especially at light load and high switching frequencies.

Multi-level converters are widely used in various industrial applications. Among various space vector modulation (SVM) schemes, the multi-level SVM scheme based on two-level space vector pulse width modulation (SVPWM) is recognised as a simplified multi-level SVM scheme, which can reduce the computation complexity. However, this scheme is still complicated when the number of the voltage levels is large. This paper proposes a modified SVM scheme that can further simplify the multi-level SVM scheme based on two-level SVPWM. The proposed SVM scheme can directly determine the two-level hexagon where the reference voltage vector is located by calculating a simple formula. The whole modulation process can be completed by only three steps. Meanwhile, the proposed method is generic for any n-level converter without adding much calculation, which greatly simplifies the modulation process. Experimental results have been provided, which verify the effectiveness and generality of the proposed SVM scheme for two types of multi-level converters.

In low and medium voltage power conversion systems, multilevel converters are becoming more and more attractive due to improved power density. However, the complexity of topology and control is a big challenge for the application of multilevel converters. In this paper, a four-level (4L) hybrid flying capacitor (FC) T-type converter has been researched in detail. The topological advantage of the converter is displayed in comparison to existing four-level converters. According to the feature of the topology, the operating status has been analyzed and the reason for the voltage jump is researched in detail during the dead-time period. A strategy to reduce voltage jump by adjusting the switching states has be presented. The FC voltages can be balanced by selecting the appropriate switching states. The relationships between the fluctuations of FC voltages and the modulation index and power factor (PF) have been analyzed by simulation results. The performance of the 4L converter has been investigated in MATLAB/Simulink as well as on a down-scaled laboratory prototype.

Multilevel converters are widely used in medium-voltage power conversion systems. In this paper, a novel five-level converter is proposed. For a three-phase system, the converter requires 30 power semiconductor devices and 12 flying capacitors in total. The required blocking voltages of all the switches are the same and the converter is suitable for medium-voltage high-power applications. A method has been proposed to control the flying capacitors' voltages. The feasibility of the proposed topology and the control method have been validated through simulation in MATLAB/Simulink.