Compared with silicon, gallium nitride, silicon carbide, and other traditional semiconductors, gallium oxide (Ga₂O₃) who possesses, an ultrawide bandgap of approximately 5.0 eV and a higher breakdown field strength of approximately 8 MV/cm has attracted increasing attention from researchers, especially for the potential application in power devices. Moreover, Ga₂O₃ material has natural ultraviolet detection ability for photodetectors due to its ultrawide bandgap. These future commercial applications put forward an urgent require for high-quality epitaxial Ga₂O₃ material in an efficient growth method at a lower cost. Although there are some conventional methods for single crystal Ga₂O₃ film epitaxial growth such as MBE and MOCVD, these methods always need a vacuum growth environment and expensive equipment. As a fast-growing method, Mist-CVD gives the growth of Ga₂O₃ in a vacuum-free, process-simple, and low-cost method, which will greatly reduce the cost and facilitate the development of Ga₂O₃. This review has summarizes the Mist-CVD epitaxy growth mechanism of Ga₂O₃, recent progress in the Ga₂O₃ film epitaxial growth, and various device properties based on the Mist-CVD method. Our work aims to provide help for the development of Ga₂O₃ material growth and device applications.

When silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) operate in the third quadrant, the surge current under extreme operating conditions hinders the body diode from replacing the external SiC Schottky barrier diode (SBD) as the freewheeling diode. Primarily, the channel activation of SiC MOSFET at $\textit{V}_\textbf{GS}$ $=$ 0 V is attributed to the body effect and the current conduction pathway within the p-well. Following this, an in-depth surge reliability analysis is conducted, contingent upon the varying structures of SiC MOSFET. The experimental result indicates that the surge capability of double-trench SiC MOSFET is inferior compared with planar SiC MOSFET and asymmetric SiC MOSFET. The impurity defects by the deep groove process and the design of the terminal layout are the critical constraints to the reliability of D-MOSFET under surge current stress. The interplay of static parameter degradation and scanning electron microscopy (SEM) investigations pinpoints two primary factors accountable for device failure. On the one hand, the gate and source terminals are short circuited due to the melting of metal electrodes caused by substantial surge currents. On the other hand, severe thermomechanical strains, incited by elevated thermal stresses attributable to surge currents, provoke substrate fissuring, and culminating in comprehensive short circuits bridging the gate, source, and drain terminals.

The dynamic avalanche reliability of 1200-V silicon carbide (SiC) power metal-oxide semiconductor field-effect transistors (MOSFETs) is studied in this article. The unclamped inductive switching (UIS) tests are conducted to locate failure points. An optimized thermal network model with the definition of the material above the epitaxial layer is used to simulate the avalanche process of SiC MOSFETs. The simulation and experiment results are matched, which verifies the validity of this model. Further simulation results show that a slight change in the doping profile of the p-well region will make the avalanche capability significantly different. Then, the effect of the deviation in cell parameters on the avalanche capability is studied by multicell simulation. The results demonstrate that uneven distribution of internal parameters makes the parasitic bipolar junction transistor (BJT) of some cells turn-on first, causing a significant concentration of current and heat in a very short time, and eventually forming hot spots often observed in failed devices.

In this article, a 4H-SiC metal-insulator-semiconductor-insulator-metal (MISIM) ultraviolet (UV) photodetector (PD) with a normal working temperature up to 550 °C, has been successfully fabricated and characterized for the first time. At 550 °C, the dark current of our fabricated MISIM remains at ~0.2 nA level and a record photo-to-dark current ratio (PDCR) of 62.7 is achieved at a reverse bias voltage of −15 V. Under 275 nm illumination, high responsivity (R) of 0.23 and 0.54 A/W have been achieved at room temperature (RT) and 550 °C, respectively. To the best of our knowledge, this is the best result reported for high-temperature UV detectors based on the 4H-SiC. This work is significant for developing high-temperature 4H-SiC-based UV PDs.

This article proposes an LED driver circuit which is wide-range continuous dimmable for high power lighting application. The proposed LED driver is based on single-inductor-multiple-output (SIMO) dc-dc converter. A pulsewidth modulation (PWM) control strategy is applied on the LED driver to control the brightness of LEDs flexibly and precisely, with which the dimming frequency can be increased significantly, and the dimming ratio for all branches can be adjusted separately. PWM dimming would cause the inductor current overshooting when dimming switch alters from off to on, which makes the LED current varying. To suppress the inductor current overshooting, a sampling-holding circuit is adopted in the feedback loop of the proposed LED driver. A prototype of the proposed LED driver is fabricated and tested. The measurement results show that the dimming frequency can be increased to 10 kHz, the dimming ratio can be set from 5% to 100% with a minimum pulsewidth of 5 μs, and the inductor current overshooting is suppressed from 150% to approximately 0%. The proposed LED driver can output more than 80 W and achieve a conversion efficiency of 97%.

High-temperature storage stressing (HTSS) experiments were carried out on high-voltage 4H-SiC junction barrier Schottky (JBS) diodes. The effects of the high-temperature (up to 275 °C) storage under air environment on thermal stability of the 4H-SiC JBS are investigated. The electrical parameter shifts for tested diodes after the HTSS were investigated in detail, and related degradation mechanisms have been discussed. It is found that HTSS has no effect on the Schottky barrier height, the ideality factor (n), and specific on-resistance (R _on-sp ). However, it was interesting that the breakdown voltage (VBR) of the devices was decreased first and then increased as the storage time increased. With the analysis of the SiO ₂ /4H-SiC interface characteristics using metal-oxide-semiconductor structure fabricated simultaneously with the investigated 4H-SiC JBS on the same wafer and technical computer-aided design (T-CAD) simulations, trapped-electrons and holes located at the interface of SiO ₂ /4H-SiC on termination region are identified to be the basic reason causing the degradation of reverse characteristics in the devices.