We investigate the GaAs0.51Sb0.49/In0.53Ga0.47As negative-capacitance vertical-tunnel FET (NCVT-FET) to maximize its vertical tunneling over the corner tunneling. Negative capacitance enhances vertical tunneling more significantly than corner tunneling due to the amplified vertical electric field. By TCAD optimization of the device, small Ioff (10 pA/μm) and large Ion (405 μA/μm) at VDD = 0.5 V with 14 mV/dec sub-Vt swing over 4 dec of current were obtained. Even at VDD =0.1 V, the optimized NCVT-FET has 10 pA/μm Ioff, 5.86 μA/μm Ion (144x higher than the nominal TFET), and Ion/Ioff ratio of 6 x 10⁵.

This paper analyzes the impacts of a single acceptor-type and donor-type interface trap induced random telegraph noise (RTN) on tunnel FET (TFET) devices and its interaction with work function variation (WFV) using atomistic 3-D TCAD simulations. Significant RTN amplitude (ΔI_D/I_D) is observed for a single acceptor trap near the tunneling junction, whereas a donor trap is found to cause more severe impact over a broader region across the channel region. In addition, several device design parameters that can be used to improve TFET subthreshold characteristics (thinner equivalent oxide thickness or longer L_eff) are found to increase the susceptibility to RTN. Our results indicate that under WFV, TFET exhibits weaker correlation between I_ON and I_OFF than that in the conventional MOSFET counterpart. In the presence of WFV, the RTN amplitude can be enhanced or reduced depending on the type of the trap and the composition/orientation of metal-gate grain.

In this work, we propose a mixed TFET-MOSFET 8T SRAM cell comprising MOSFET cross-coupled inverters, dedicated TFET read stack and TFET write access transistors for ultra-low voltage operation. Exploiting both the merits of TFET and MOSFET devices, the proposed SRAM cell provides significant improvement in SRAM stability, Vmin and performance. The stability and performance of the proposed cell are evaluated and compared with the conventional MOSFET 8T cell and pure TFET 8T cell using mixed-mode TCAD simulations based on published design rules for 22 nm technology node. Besides, the impacts of the device design of the proposed SRAM cell on the stability are also investigated. Various write-assist techniques to enhance the write-ability across VDD= 0.2 to 0.7 V for these SRAM cells are comparatively assessed. The results indicate that the proposed mixed TFET-MOSFET cell topology is viable for ultra-low voltage operation while MOSFET cell provides better stability and performance for high voltage operation.

This paper analyzes the impacts of single-charged-trap-induced random telegraph noise (RTN) on FinFET devices in tied- and independent-gate modes, 6T static random access memory (SRAM) cell stability, and several basic logic circuits. The dependence of RTN on trap location, EOT, and temperature is evaluated through 3-D atomistic TCAD simulation. It is observed that the charged trap located near the bottom of sidewall (gate) interface and in the middle region between the source and drain will result in the most significant impact. EOT scaling and higher operating temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependence on the location of the trap and bias-dependent current-conduction path are analyzed. We show that the planar BULK device, with larger subthreshold swing ($S.S.$) and comparable trap-induced $V_{T}$ shift, exhibits less nominal RTN degradation than FinFET for traps placed in the worst position. However, the larger variability and surface conduction characteristic of the planar BULK device lead to broader dispersion and larger worst case RTN degradation than the FinFET device with smaller variability and volume conduction. For traps randomly placed across the interface, similar RTN amplitude dispersions are observed for FinFET and planar BULK devices except in the vicinity of distribution tail due to the strong interaction between the charged trap and discrete random dopants in planar BULK devices. For 6T FinFET SRAM cell, the READ static noise margin of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage $(V_{\rm dd})$, the importance of RTN on subthreshold cell stability increases. Moreover, the leakage and delay of FinFET inverters, two-way nand, and two-to-one multiplexer are investigated using 3-D TCAD mixed-mode simulations. The RTN is found to cause $\sim$24%–27% and $\sim$13%–15% variations in leakage and delay at $V_{ \rm dd} = \hbox{0.4}\ \hbox{V}$, respectively, for the logic circuits evaluated.

HfO₂-based ferroelectric (FE–HfO₂) is a promising material for low-power and high-capacity memory technology. Since thinner ferroelectric films are required for low voltage operation, the impact of film thickness on the switching kinetics of FE–HfO₂ needs to be studied in detail. In this paper, metal/ferroelectric/metal capacitors are fabricated with several thicknesses of HfZrO₂ (HZO) films and characterized to study the switching kinetics based on the nucleation limited switching (NLS) model. Thinner HZO capacitors show slower polarization switching and asymmetry in program and erase operation, although low-frequency polarization charge density is nearly the same for all thicknesses. Slow switching is due to the large variability of the activation field of FE domains and grain boundaries among small FE grains. The asymmetry is caused by the asymmetric interface property at the top and bottom interfaces. High-resolution TEM and electron diffraction mapping methods provide physical evidence for the above discussions.