This paper presents a linear-mode optical sensor for the feasible applications of unmanned vehicle LiDAR systems, in which a pulsed-erbium fiber laser is exploited as a light source and a 16-channel transimpedance amplifier (TIA) array is utilized in an optical Rx module with low-cost InGaAs PIN photodiodes. In particular, a voltage-mode CMOS feedforward (VCF-TIA) is newly proposed to achieve twice higher transimpedance gain with lower noise and similar bandwidth characteristics than a conventional inverter TIA, thereby enabling longer detection. Test chips of the 16-channel VCF-TIA array realized in a standard 0.18-μm CMOS process demonstrate 76.3-dBΩ transimpedance gain, 6.3-pA/sqrt(Hz) average noise current spectral density, less than -33-dB crosstalk between channels, and 29.8-mW power dissipation per channel from a single 1.8-V supply. Automatic gain control is also equipped to extend input dynamic range for near-range detection. Hence, the proposed linear-mode optical sensor clearly detects the reflected optical pulses from the target of 5% reflection rate within the range of 0.5-25 m.

We present a real-time electroencephalogram (EEG) based depth of anesthesia (DoA) monitoring system in conjunction with a deep learning framework, AnesNET. An EEG analog front-end (AFE) that can compensate ±380-mV electrode DC offset using a coarse digital DC servo loop is implemented in the proposed system. The EEG-based MAC, EEGMAC, is introduced as a novel index to accurately predict the DoA, which is designed for applying to patients anesthetized by both volatile and intravenous agents. The proposed deep learning protocol consists of four layers of convolutional neural network and two dense layers. In addition, we optimize the complexity of the deep neural network (DNN) to operate on a microcomputer such as the Raspberry Pi 3, realizing a cost-effective small-size DoA monitoring system. Fabricated in 110-nm CMOS, the prototype AFE consumes 4.33 μW per channel and has the input-referred noise of 0.29 μVrms from 0.5 to 100 Hz with the noise efficiency factor of 2.2. The proposed DNN was evaluated with pre-recorded EEG data from 374 subjects administrated by inhalational anesthetics under surgery, achieving an average squared and absolute errors of 0.048 and 0.05, respectively. The EEGMAC with subjects anesthetized by an intravenous agent also showed a good agreement with the bispectral index value, confirming the proposed DoA index is applicable to both anesthetics. The implemented monitoring system with the Raspberry Pi 3 estimates the EEGMAC within 20 ms, which is about thousand-fold faster than the BIS estimation in literature.

We proposed a high-performance elliptic curve cryptography (ECC) processor over NIST prime fields. Instead of applying a full modular reduction to a 2k-bit product, the proposed partial modular reduction method iteratively performs reductions on partial products whose bit length is slightly greater than k, where k is the bit length of field elements. As a result, the computational complexity of modular multiplication (MM) was significantly reduced. Moreover, the amount of computation is configurable by parameterizing the size of the partial products. This is a very desirable characteristic of the proposed ECC processor, because the hardware complexity and processing time of the entire ECC processor can be adjusted according to the requirements of various Internet of Things environments. Including the proposed MM module, finite field operation modules are integrated into a single module to further reduce the required resources. The proposed ECC processor synthesized using 180-nm CMOS process technology can perform a 256-bit elliptic curve point multiplication in 0.20-0.74 ms with 144.8k- 65.4k gate counts. These results and the experimental results in various FPGA devices show that the proposed ECC processor has significantly better throughput per area than the previously reported ones.

To overcome light interference, including a large DC offset and ambient light variation, a robust photoplethysmogram (PPG) readout chip is fabricated using a 0.13-μm complementary metal–oxide–semiconductor (CMOS) process. Against the large DC offset, a saturation detection and current feedback circuit is proposed to compensate for an offset current of up to 30 μA. For robustness against optical path variation, an automatic emitted light compensation method is adopted. To prevent ambient light interference, an alternating sampling and charge redistribution technique is also proposed. In the proposed technique, no additional power is consumed, and only three differential switches and one capacitor are required. The PPG readout channel consumes 26.4 μW and has an input referred current noise of 260 pArms.

An impulse radio ultra-wideband (IR-UWB) transceiver is implemented with low power, high data rate communication techniques, such as extended multipulse position modulation (E-MPPM), cross-coupled (CC) envelope detection, and digital frequency hopping (DFH). The use of the E-MPPM helps increase the modulation efficiency. The capacitive-CC technique helps improve the sensitivity by increasing the conversion gain of an envelope detector. DFH increases the pulse energy of a transmitted impulse without sacrificing the power spectral density (PSD) requirement. The proposed CMOS transceiver achieves a data rate of 1.125 Gbps and a radio range of 2 m with a power consumption of 28 mW and energy efficiency of 24.9 pJ/b.