The cold source field-effect transistor (CSFET), enabled by novel source engineering, is a promising alternative to achieve sub-60 mV/dec steep-slope switching. For the first time, we develop an industry-standard TCAD approach for the CSFET with an effective cold carrier density of states (DOS) model which captures the underlying physics of DOS engineering, cold carrier injection, and thermalization in the device. The simulation scheme uses nonequilibrium Green's function (NEGF) simulation for calibration. The effects of source engineering, rethermalization, and channel tunneling are extensively investigated on a Si-based double-gate CSFET. Its merits are highlighted by comparison with a conventional MOSFET under various temperatures, thicknesses, and gate lengths, showing improved Ion/Ioff in ultrascaled MOSFET.

In this article, an analytical thermal conductivity model for confined nanochannel in gate-all-around silicon nanowire field-effect transistors (GAA SiNW FETs) is developed by considering the limitations caused by the cross section and length. A geometry dependence of phonon mean free path (MFP) is established for quantitatively analyzing the influence of cross-sectional dimension. Furthermore, the length-induced degradation mechanism is revealed by employing the transverse transportation phonon effective MFP. The results calculated by the model which was verified by published data indicate that the thermal conductivity of confined nanochannel in the GAA SiNW FETs is suffering from a severe degradation compared to that of ultrathin silicon in fully depleted (FD) silicon-on-insulator (SOI) MOSFETs. In addition to the suppression caused by the cross-sectional boundaries, the impact of the channel length should be taken into consideration during the modeling of thermal conductivity for accurately evaluating the self-heating effects (SHEs) in GAA SiNW FETs.

To quantitatively describe the inflection and the recently observed protrusion phenomenon in the subthreshold region at cryogenic temperature, this study presents a novel model featuring a Gaussian-distributed band tail, combining the Gaussian interface state positioned away from the energy band. The Gaussian band tail can capture the inflection phenomenon of low-temperature subthreshold swing (SS), and the introduction of the interface state in the forbidden band enables accurate modeling of the SS protrusion. The proposed model can favorably describe ${I}_{\text {DS}}$ – ${V}_{\text {GS}}$ , SS– ${I}_{\text {DS}}$ , and SS– ${T}$ spanning from 10 to 300 K of the commercial 0.35- $\mu \text{m}$ bulk n/p- MOSFET and 14-nm n-FinFET technology, potentially enabling a unified method of capturing the SS of a MOSFET at the cryogenic temperature.

In this article, an analytical thermal conductivity model considering the degradation caused by the different phonon scattering mechanisms is presented for studying the self-heating effects (SHEs) in ultrathin body and buried oxide (UTBB) silicon-on-insulator (SOI) MOSFETs. By allowing for phonon-boundary and phonon–electron scattering, as well as tuning the surface roughness, the model enables accurate predictions for silicon films of different thicknesses over a wide temperature range. In order to apply the temperature-dependent self-built thermal conductivity model to the technology computer-aided design (TCAD) electrothermal simulation, a piecewise fitting, and equivalent strategy is developed by using the zero points (ZPs) and extreme points (EPs) of the first- and second-order discrete differentials of the model. The results show that the modified model is closer to the experimental data from literature studies than the default TCAD model in predicting the thermal conductivity distribution of the SOI-structure. Furthermore, the TCAD simulation results with our modified model show the same trend as that with its default model in predicting the performance degradation of UTBB SOI devices due to SHEs, such as the degradation of carrier mobility in the channel and the increase of subthreshold swing (SS).

Source engineering is an emerging technique to achieve steep-slope switching FET. To bridge the new carrier filtering mechanism and device performance, a multiscale simulation framework is presented in this article and is applied in Si nanowire (NW) cold source FET (CSFET). By the fit-parameter-free density functional theory (DFT) method, the key component of cold source (CS) design for broken-gap-like band alignment and high cold carrier injection is demonstrated. The novel device switching mechanism is also verified in the entire device scale with fully quantum atomistic tight-binding (TB) and nonequilibrium Green’s function (NEGF) methods. Although these tools are physics-based and accurate, the device scale is limited, and the computation burden is heavy. Thus, half-empirical TCAD simulation is suitable for device design and path-finding in realistic geometry. Key components of the CS and energy filtering effect can be verified by DFT-NEGF and TB-NEGF methods. Based on TCAD results, we implement a circuit-level benchmark for early stage path-finding. The results show that gate-all-around (GAA) Si NW CSFET is a potential candidate for low-power application, which enables supply voltage scaling.

The silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) suffer intensive self-heating effects due to the reduced thermal conductivity of the silicon layer while the feature sizes of devices scale down to the nanometer regime. In this work, analytical models of thermal conductivity considering the self-heating effect (SHE) in ultra-thin body fully depleted (UTB-FD) SOI MOSFETs are presented to investigate the influences of impurity, free and bound electrons, and boundary reflection effects on heat diffusion mechanisms. The thermal conductivities of thin silicon films with different parameters, including temperature, depth, thickness and doping concentration, are discussed in detail. The results show that the thermal dissipation associated with the impurity, the free and bound electrons, and especially the boundary reflection effects varying with position due to phonon scattering, greatly suppressed the heat loss ability of the nanoscale ultra-thin silicon film. The predictive power of the thermal conductivity model is enhanced for devices with sub-10-nm thickness and a heavily doped silicon layer while considering the boundary scattering contribution. The absence of the impurity, the electron or the boundary scattering leads to the unreliability in the model prediction with a small coefficient of determination.