The self-heating ,effects in vacuum gate dielectric gate-all-around field effect transistors (GAA FETs) with vertically stacked 4-nm silicon nanowire (SiNW) channels are investigated by 3-D TCAD simulation. The cross-sectional dimension-dependent thermal conductivity model of the SiNW is proposed for the precise numerical simulation of self-heating effects based on the temperature-dependent thermal conductivity of the bulk silicon. The thermal conductivity model which was verified by published data indicates that thermal conductivity of 4-nm SiNW is greatly reduced to below 10 W/mK due to the pronounced phonon boundary scattering. Simulation results shows that the vacuum gate dielectric devices undergo more severe self-heating effects than the solid gate dielectric GAA SiNW FETs, resulting in more serious performance degradation. Multiple heat sources generated by the three-stacked SiNWs make heat generation and diffusion more difficult. An effective method is proposed to suppress the self-heating effects by increasing the spacing of the gas gap within in a certain range and the around ambient gas pressure.

In this article, an analytical thermal conductivity model for confined nanochannel in gate-all-around silicon nanowire field-effect transistors (GAA SiNW FETs) is developed by considering the limitations caused by the cross section and length. A geometry dependence of phonon mean free path (MFP) is established for quantitatively analyzing the influence of cross-sectional dimension. Furthermore, the length-induced degradation mechanism is revealed by employing the transverse transportation phonon effective MFP. The results calculated by the model which was verified by published data indicate that the thermal conductivity of confined nanochannel in the GAA SiNW FETs is suffering from a severe degradation compared to that of ultrathin silicon in fully depleted (FD) silicon-on-insulator (SOI) MOSFETs. In addition to the suppression caused by the cross-sectional boundaries, the impact of the channel length should be taken into consideration during the modeling of thermal conductivity for accurately evaluating the self-heating effects (SHEs) in GAA SiNW FETs.

In this article, an analytical thermal conductivity model considering the degradation caused by the different phonon scattering mechanisms is presented for studying the self-heating effects (SHEs) in ultrathin body and buried oxide (UTBB) silicon-on-insulator (SOI) MOSFETs. By allowing for phonon-boundary and phonon–electron scattering, as well as tuning the surface roughness, the model enables accurate predictions for silicon films of different thicknesses over a wide temperature range. In order to apply the temperature-dependent self-built thermal conductivity model to the technology computer-aided design (TCAD) electrothermal simulation, a piecewise fitting, and equivalent strategy is developed by using the zero points (ZPs) and extreme points (EPs) of the first- and second-order discrete differentials of the model. The results show that the modified model is closer to the experimental data from literature studies than the default TCAD model in predicting the thermal conductivity distribution of the SOI-structure. Furthermore, the TCAD simulation results with our modified model show the same trend as that with its default model in predicting the performance degradation of UTBB SOI devices due to SHEs, such as the degradation of carrier mobility in the channel and the increase of subthreshold swing (SS).

The silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) suffer intensive self-heating effects due to the reduced thermal conductivity of the silicon layer while the feature sizes of devices scale down to the nanometer regime. In this work, analytical models of thermal conductivity considering the self-heating effect (SHE) in ultra-thin body fully depleted (UTB-FD) SOI MOSFETs are presented to investigate the influences of impurity, free and bound electrons, and boundary reflection effects on heat diffusion mechanisms. The thermal conductivities of thin silicon films with different parameters, including temperature, depth, thickness and doping concentration, are discussed in detail. The results show that the thermal dissipation associated with the impurity, the free and bound electrons, and especially the boundary reflection effects varying with position due to phonon scattering, greatly suppressed the heat loss ability of the nanoscale ultra-thin silicon film. The predictive power of the thermal conductivity model is enhanced for devices with sub-10-nm thickness and a heavily doped silicon layer while considering the boundary scattering contribution. The absence of the impurity, the electron or the boundary scattering leads to the unreliability in the model prediction with a small coefficient of determination.

An improved physical model was proposed for accurate electrothermal modeling Pirani vacuum gauges (PVG) by accounting for the micro-nano scale effects of heat transfer in sensitive elements and the non-negligible corner heat dissipation from multiple heat sinks. This model is verified by published experimental data and can reveal the influences of geometrical, physical and process parameters, such as device dimensional size, temperature and doping concentrations, on the micro-nano scale heat transfer process, which is a great consideration for microelectromechanical systems (MEMS) PVG designing. Although the model is initially envisaged for MEMS PVG, it could be straightforwardly adopted for the thermal sensors with silicon heaters. Finally, the characteristics of PVG were comprehensively investigated based on the presented model validated by the experimental data. The results show that expanding the area ratio of heat sinks to heater and the thermal resistance ratio of heater to gas is an effective design idea to optimise the maximum sensitivity and central pressure of device.

A 320 $\times $ 240 indirect time-of-flight (i-ToF) image sensor with a 5.6- $\mu \text{m}$ two-tap 1.5-V pump gate modulation pixel has been designed. Novel characteristics, such as the optimized pinned layer doping and potential buffer region (PBR) structure with pump gate modulator (PGM), are proposed to achieve a maximum lateral modulation electric field of 1500 V/cm under the front-side illumination (FSI) process. As a result, the proposed time-of-flight (ToF) sensor shows 200-mW power consumption and 54% demodulation contrast (DC) at 50-MHz modulation frequency, depth noise less than 1% with 940-nm illuminator from 0.3 to 3 m.