Wafer bonding of a silicon carbide (SiC) diaphragm to a patterned SiC substrate coated with aluminum nitride (AlN) film as an insulating layer is a promising choice to fabricate an all-SiC capacitive pressure sensor. To demonstrate the bonding feasibility, a crystalline AlN film with a root-mean-square (RMS) surface roughness less than ~0.70 nm was deposited on a SiC wafer by a pulsed direct current magnetron sputtering method. Room temperature wafer bonding of SiC-AlN by two surface activated bonding (SAB) methods (standard SAB and modified SAB with Si nano-layer sputtering deposition) was studied. Standard SAB failed in the bonding, while the modified SAB achieved the bonding with a bonding energy of ~1.6 J/m². Both the microstructure and composition of the interface were investigated to understand the bonding mechanisms. Additionally, the surface analyses were employed to confirm the interface investigation. Clear oxidation of the AlN film was found, which is assumed to be the failure reason of direct bonding by standard SAB.

The effects of low oxygen partial pressure (low-p _O2 ) annealing and NO annealing on both performance and reliability of silicon carbide (SiC) MOS capacitors are verified, and the sequential annealing in low-p _O2 and NO is also investigated. The sequential annealing is effective to improve the reliability of SiC MOS capacitors but shows slight deterioration of interface property. The results show that annealing in the atmosphere of low partial pressure oxygen changes the distribution of defect about the SiO ₂ /SiC interface, and influences the following NO annealing effect. The mechanism of oxidation and annealing is discussed, and some suggestions on annealing are given. This experiment provides some inspiration for the combination of annealing processes and the optimization of annealing conditions.

The paper investigated the annealing temperature dependence of electrical and structural properties for Ni (50 nm)/Ti (60 nm)/W (60 nm) Ohmic contacts simultaneously formed on n- and p-type 4H-SiC by in-depth electrical and physical characterization. With the annealing temperature rising in the range of 900 °C–1050 °C, the specific contact resistances (SCRs) of both n- and p-type Ohmic contacts monotonously decreased with a similar trend in the range of 1 × 10⁻⁴–1 × 10⁻⁶ Ω cm², which was favorable for the simultaneous formation of n- and p-type Ohmic contacts with lower SCRs in the active region. For n-type Ohmic contacts, the variation of SCRs with annealing temperatures was correlated to the relative proportion of the total contact area occupied by the (220) plane compared to the other planes for the polycrystalline and textured δ-Ni₂Si film at the contact interface characterized by x-ray diffraction. Furthermore, the surface morphology of Ohmic contacts under different annealing temperatures was highly similar with almost identical root mean square roughness of about 6.2 nm measured by atomic force microscopy (AFM), which was thought to be smooth enough for the wire bonding process from the perspective of device applications. The distinct W layer with no evidence of obvious intermixing and the great distance of released free carbon away from the contact surface makes the surface morphology smooth and uniform.

The interface states and reliability of 4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs) with thermal gate oxides have been researched widely. Several reports have researched the gate oxide process itself, but the effects of subsequent processes should not be ignored. In this paper, the reliability of thermal gate oxide films followed by polysilicon gate (poly-gate) process, which are widely used in MOSFET manufacture, and Al gates were compared. The poly-gate samples markedly affected the performance measured by time-zero dielectric breakdown and time-dependent dielectric breakdown methods because the phosphorus content diffused during poly-gate formatting; this was especially advantageous in reducing leakage current and improving the charge-to-breakdown (Q _BD). After electronic characteristics measurements, scanning electron microscopy cross-sections were also used to analyze the breakdown mechanism. We observed an intermediate layer between the Al gate and the oxide that may cause the barrier height to be smaller than that of the poly-gate. The Al work function and polysilicon Fermi level determine the gate leakage currents and the resultant gate oxide reliability, whereas the Al₂O₃ gate sample has a smaller work function offset (0.7 eV) than ideal Al gate and poly-gate samples. The results imply that the reliability of the Al gate samples may be an intrinsic problem.