This paper aims to compare different design alternatives of hardware-in-the-loop (HIL) for emulating power converters in Field Programmable Gate Arrays (FPGAs). It proposes various numerical formats (fixed and floating-point) and different approaches (pure VHSIC Hardware Description Language (VHDL), Intellectual Properties (IPs), automated MATLAB HDL code, and High-Level Synthesis (HLS)) to design power converters. Although the proposed models are simple power electronics HIL systems, the idea can be extended to any HIL system. This study compares the design effort of different coding methods and numerical formats considering possible synthesis tools (Precision and Vivado), and it comprises an analytical discussion in terms of area and speed. The different models are synthesized as ad-hoc modules in general-purpose FPGAs, but also using the NI myRIO device as an example of a commercial tool capable of implementing HIL models. The comparison confirms that the optimum design alternative must be chosen based on the application (complexity, frequency, etc.) and designers’ constraints, such as available area, coding expertise, and design effort.

Real-time Hardware-In-the-Loop implementations for power converters involve digital sampling of the on-off signals that are applied to the switches. The most basic way of considering it, is to process only one switch state during a simulation step. This usually causes an incorrect input reading because it can change during the step. The negative effects include the appearance of undesirable subharmonics and numerical inaccuracy. In this work, input signal oversampling is proposed. Thus, several switch states can be properly processed within the same simulation step. The question is how to use this additional information. This paper proposes two oversampling approaches: a sequential one, which is based on previous works, and a parallel implementation, which is the main contribution of the paper. The results obtained with these techniques are compared between them and with the model without oversampling, showing a significant increase in accuracy for both oversampling approaches around 98%. Although the accuracy is very similar in both methods, synthesis results for FPGA implementation are clearly better for the parallel method, which can be easily adapted to process multiple switching events. The final experimental results show a great subharmonic decrease up to 99%.

The FPGA (Field Programmable Gate Array) implementation of real-time Hardware-In-the-Loop techniques is constantly growing due to its high speed. However, hardware implementation of SMPS (Switched-Mode Power Supplies) introduces some challenges, because their equations are changed depending on the state of the switches. This becomes more important in multistep numerical methods, which use several previous values. This letter presents the implementation scheme of Adams-Bashforth method which allows the designer to correctly apply it to switching power converters. The global accuracy and utilization results of the approach are analyzed in the letter. The results show that the proposed modification makes sense due to the high accuracy improvement at the expense of a reasonable increase in resources.

The use of Hardware-in-the-Loop (HIL) systems implemented in Field Programmable Gate Arrays (FPGAs) is constantly increasing because of its advantages compared to traditional simulation techniques. This increase in usage has caused new challenges related to the improvement of their performance and features like the number of output channels, while the price of HIL systems is diminishing. At present, the use of low-speed Digital-to-Analog Converters (DACs) is starting to be a commercial possibility because of two reasons. One is their lower price and the other is their lower pin count, which determines the number and price of the FPGAs that are necessary to handle those DACs. This paper compares four filtering approaches for providing suitable data to low-speed DACs, which help to filter high-speed input signals, discarding the need of using expensive high-speed DACS, and therefore decreasing the total cost of HIL implementations. Results show that the selection of the appropriate filter should be based on the type of the input waveform and the relative importance of the dynamics versus the area.

Hardware-In-the-Loop (HIL) has become a popular technique for testing real-time complex systems.One of its possible applications is power converter modeling in order to test digital controllers.When a switching converter model is used, the output of the controller can be read incorrectly by the model due to the lack of synchronization of their clocks.Therefore, undesirable oscillations (subharmonics) can appear in the output due to the aliasing effects, which prevent the HIL model from its normal functionality.While there are various solutions present in academic and industrial research in order to address this arising problem, there is no automatic algorithm to detect it when a reference model is not available. In this paper, we implement a one-dimensional convolutional neural network which allows detecting the aliasing distortions.The 1D network was chosen due to the kind of the signal to be classified - an inductor current of the converter model, which is in effect a 1D time sequence.The proposed CNN architecture is shallow and consists of 27 layers only.Despite its simplicity, it shows remarkable performance of more than 99% for both validation and testing datasets, and for the post-training characteristics.Moreover, it makes the architecture potentially implementable in embedded systems, like a real-time HIL system, what can be a good objective for future research.

Common implementations of power factor correction include sensors for the input and output voltages and the input current. Many alternatives have been considered to reduce the number of sensors, especially the current sensor. One strategy is to precalculate the duty cycles that must be applied to every ac main, so the system only needs to synchronize them with the input voltage, and include a simple output voltage loop. The main problem with this approach is the sensibility to any synchronization error, because the input current is not measured, so its evolution is not continuously corrected. This paper shows how the synchronization error alters the current and the power factor, and it proposes several methods to detect and correct this error. All methods use the output voltage ADC, which is already used to control the output voltage, so the cost of the system is not increased. This technique can also be applied to any current sensorless PFC converter, because they are usually affected by leading or lagging currents, so the synchronization can be modified to reduce these effects. Results show that the implementation of this synchronization loop keeps a high-power factor under a wide synchronization error range, while the added logic is not significant.