We present a hybrid pipelined sorting architecture capable of finding and producing as its output the K largest elements from an input sequence. The architecture consists of a bitonic sorter and L cascaded sorting units. The sorting unit is designed to output P elements during every cycle with the aim of increasing the throughput and lowering the latency. The function of the bitonic sorter is to generate a segmented ordered sequence. The sorting unit processes this sequence to identify and output the P largest elements. Hence, the K=PL largest elements are obtained after the segmented ordered sequence proceeds through L cascaded sorting units. Variable-length and continuous sequences are supported by the proposed sorting architecture. The results of the implementation show that the sorting architecture can achieve a throughput of 22.88 GB/s with P=16 on a state-of-the-art Field Programmable Gate Array (FPGA).

The offloading and acceleration of database operations on field programmable gate arrays (FPGAs) have been extensively studied for a long time. Architectures of join, a key database operation, have been proposed and optimized on FPGAs. However, these join architectures are either resource-intensive or have low-throughput. In this paper, we focus on the equi-join and propose a resource-efficient join architecture based on a tree model. The architecture needs two phases: the build phase, in which a binary tree is built by using the first database table, and the probe phase, in which the architecture searches the tree to find matching solutions through a second database table. In addition, we propose a parallel implementation for this architecture to improve its performance. The proposed design was implemented on a Xilinx FPGA, and the results were compared with the most recent works on hardware join. The experimental results demonstrate that for a range of parallelism and dataset sizes, our design achieves a data throughput of 8–100 million tuples per second, which is compatible with the bus rate, and performs well in balancing resource utilization and data throughput.

Switches play a critical role as core components in data center networks. The advent of multi-die chiplet packaging as a prevailing trend in complex chip development presents challenges in designing the multi-die packaging of switch chips. With limited inter-die connections in mind, we propose a scalable, unified switch architecture optimized for efficient connectivity. This architecture includes the strategic mapping of data queues, meticulous planning of data paths, and the integration of a unified interface, all aiming to facilitate efficient switch operations within constrained connectivity environments. Our optimization efforts encompass various areas, including refining arbitration strategies, managing mixed unicast and multicast transmissions, and mitigating network congestion to alleviate bottlenecks in data flow. These enhancements contribute to heightened levels of performance and robustness in the switching process. During the validation phase, the structure we propose reduced interconnection usage between dies by 25%, while supporting functions such as unicast and multicast transmissions.

This brief proposes a join algorithm based on a top k-sorter. The algorithm applies a filter to remove tuples having no potential matches with the aim of reducing the number of comparisons during join operations between two tables (Ta,Tb). Based on this algorithm, we designed a modular pipeline join architecture that comprises k cascaded processing units. The resource consumption of the architecture is unaffected by the table size such that a join operation between tables with arbitrary sizes is supported. The join process includes a loop in which the k “largest" tuples of the table with smaller size (Ta) are identified to match and filter the tuples of the other table (Tb). Each tuple of Tb is compared with the k largest tuples in turn and discarded if a “smaller" tuple is encountered. After each iterative cycle, the k largest tuples of Ta are also removed. The loop terminates once either of the two tables becomes empty. The experimental results show that the proposed join architecture is not only resource efficient but also achieves high throughput on a state-of-the-art Field Programmable Gate Array (FPGA).

Sorting is one of the most fundamental problems in mathematics and computer science. Because high-throughput and flexible sorting is a key requirement in modern databases, this paper presents efficient techniques for designing a high-throughput sorting matrix that supports continuous data sequences. There have been numerous studies on the optimization of sorting circuits on FPGA (field-programmable gate array) platforms. These studies focused on attaining high throughput for a single command with fixed data width. However, the architectures proposed do not meet the requirement of diversity for database data types. A sorting matrix architecture is thus proposed to overcome this problem. Our design consists of a matrix of identical basic sorting cells. The sorting cells work in a pipeline and in parallel, and the matrix can simultaneously process multiple data streams, which can be combined into a high-width single-channel data stream or low-width multiple-channel data streams. It can handle continuous sequences and allows for sorting variable-length data sequences. Its maximum throughput is approximately 1.4 GB/s for 32-bit sequences and approximately 2.5 GB/s for 64-bit sequences on our platform.