This paper proposes a synaptic device based on charge-trap flash memory that has good CMOS compatibility and superior reliability characteristics compared with other synaptic devices. Using hot-electron injection and hot-hole injection, we designed operation methods to implement gradual conductance modulation and spike-timing-dependent plasticity. We demonstrate the feasibility of the device for neuromorphic applications through both a device-level technology computer-aided design simulation and a system-level MATLAB simulation. For the first time, we also propose a 3-D stacked synapse array and present the structure, operation, and process methods. The proposed array architecture features a small area and low process cost and could be a novel solution for neuromorphic systems for implementing deep neural networks.

Various memory devices have been proposed for implementing synapse devices in neuromorphic systems. In this paper, an AND flash array based on charge trap flash (CTF) memory was proposed. CTF-based synapse devices are particularly suitable for off-chip learning applications because they have excellent reliability and stable multi-level operation characteristics. In addition, we proposed a method to implement convolutional neural networks in the proposed array, and performed system-level simulation using the characteristics of the fabricated device. Finally, we investigated the accuracy degradation of the neuromorphic system related to data retention and proposed a multiple cell mapping scheme to address this degradation issue.

This paper proposes a 3-D floating-gate (FG) synapse array for neuromorphic applications. The designed device has certain advantages over previous planar FG synapse devices: a smaller cell size due to the stacked structure and smaller operation voltage by the gate-all-around geometry. In addition, the operation method to implement spike time-dependent plasticity is proposed and demonstrated. The proposed array based on commercialized flash memory technology is expected be one of the most promising candidate architecture for neuromorphic applications.

In order to address a fundamental bottleneck of conventional digital computers, there is recently a tremendous upsurge of investigations on hardware-based neuromorphic systems. To emulate the functionalities of artificial neural networks, various synaptic devices and their 2-D cross-point array structures have been proposed. In our previous work, we proposed the 3-D synapse array architecture based on a charge-trap flash (CTF) memory. It has the advantages of high-density integration of 3-D stacking technology and excellent reliability characteristics of mature CTF device technology. This paper examines some issues of the 3-D synapse array architecture. Also, we propose an improved structure and programming method compared to the previous work. The synaptic characteristics of the proposed method are closely examined and validated through a technology computer-aided design (TCAD) device simulation and a system-level simulation for the pattern recognition task. The proposed technology will be the promising solution for high-performance and high-reliability of neuromorphic hardware systems.

Resistive random-access memories (RRAMs) based on metal-oxide thin films have been studied extensively for application as synaptic devices in neuromorphic systems. The use of graphene oxide (GO) as a switching layer offers an exciting alternative to other materials such as metal-oxides. We present a newly developed RRAM device fabricated by implementing highly-packed GO layers on a highly doped Si wafer to yield a gradual modulation of the memory as a function of the number of input pulses. By using flow-enabled self-assembly, highly uniform GO thin films can be formed on flat Si wafers in a rapid and simple process. The switching mechanism was explored through proposed scenarios reconstructing the density change of the sp ² cluster in the GO layer, resulting in a gradual conductance modulation. We analyzed that the current in a low resistance state could flow by tunneling or hopping via clusters because the distance between the sp ² clusters in closely-packed GO layers is short. Finally, through a pattern-recognition simulation with a Modified National Institute of Standards and Technology database, the feasibility of using close-packed GO layers as synapse devices was successfully demonstrated.

Impact ionization and hot-carrier degradation (HCD) in buried-channel-array transistors (BCATs), which are used as the cell transistor, were investigated using sub-30 nm DRAM technology. The impact ionization rate was calculated by measuring the substrate current at different measurement conditions and modeled using an energy-driven model, which is suitable for short-channel transistors. In addition, HCD in BCAT under various operation conditions was analyzed. A multitrap-based approach, in which both interface- and oxide-trap generation were considered, was used to fit the experimental results. Our analysis and modeling results are useful in understanding and predicting the reliability of dynamic random access memory.