The vertical Gallium Nitride-on-Silicon (GaN-on-Si) trench metal-oxide-semiconductor field effect transistor (MOSFET) is a promising architecture for the development of efficient GaN-based power transistors on foreign substrates for power conversion applications. This work presents an overview of recent case studies, to discuss the most relevant challenges related to the development of reliable vertical GaN-on-Si trench MOSFETs. The focus lies on strategies to identify and tackle the most relevant reliability issues. First, we describe leakage and doping considerations, which must be considered to design vertical GaN-on-Si stacks with high breakdown voltage. Next, we describe gate design techniques to improve breakdown performance, through variation of dielectric composition coupled with optimization of the trench structure. Finally, we describe how to identify and compare trapping effects with the help of pulsed techniques, combined with light-assisted de-trapping analyses, in order to assess the dynamic performance of the devices.

We present a first study of threshold voltage instabilities of semi-vertical GaN-on-Si trench-MOSFETs, based on double pulsed, threshold voltage transient, and UV-assisted C–V analysis. Under positive gate stress, small negative V _th shifts (low stress) and a positive V _th shifts (high stress) are observed, ascribed to trapping within the insulator and at the metal/insulator interface. Trapping effects are eliminated through exposure to UV light; wavelength-dependent analysis extracts the threshold de-trapping energy ≈2.95 eV. UV-assisted CV measurements describe the distribution of states at the GaN/Al₂O₃ interface. The described methodology provides an understanding and assessment of trapping mechanisms in vertical GaN transistors.

We propose to use a bilayer insulator (2.5 nm Al₂O₃ + 35 nm SiO2) as an alternative to a conventional uni-layer Al₂O₃ (35 nm), for improving the performance and the reliability of GaN-on-Si semi vertical trench MOSFETs. This analysis has been performed on a test vehicle structure for module development, which has a limited OFF-state performance. We demonstrate that devices with the bilayer dielectric present superior reliability characteristics than those with the uni-layer, including: (i) gate leakage two-orders of magnitude lower; (ii) 11 V higher off-state drain breakdown voltage; and (iii) 18 V higher gate-source breakdown voltage. From Weibull slope extractions, the uni-layer shows an extrinsic failure, while the bilayer presents a wear-out mechanism. Extended reliability tests investigate the degradation process, and hot-spots are identified through electroluminescence microscopy. TCAD simulations, in good agreement with measurements, reflect electric field distribution near breakdown for gate and drain stresses, demonstrating a higher electric field during positive gate stress. Furthermore, DC capability of the bilayer and unilayer insulators are found to be comparable for same bias points. Finally, comparison of trapping processes through double pulsed and V_th transient methods confirms that the V_th shifts are similar, despite the additional interface present in the bilayer devices.

Developing high quality GaN/dielectric interfaces is a fundamental step for manufacturing GaN vertical power transistors. In this paper, we quantitatively investigate the effect of planar etching treatment and trench formation on the performance of GaN-based MOS (metal oxide semiconductor) stacks. The results demonstrate that (i) blanket etching the GaN surface does not degrade the robustness of the deposited dielectric layer; (ii) the addition of the trench etch, while improving reproducibility, results in a decrease in the breakdown performance compared to the planar structures. (iii) For trench structures, the voltage for a 10 year lifetime is still above 20 V, indicating a good robustness. (iv) To review the trapping performance across the metal-dielectric-GaN stack, forward-reverse capacitance–voltage measurements with and without stress and photo-assistance are performed. Overall, as-grown planar capacitors devoid of prior etching steps show the lowest trapping, while trench capacitors have higher interface trapping and bulk trapping comparable to the blanket etched capacitors. (v) The nanostructure of the GaN/dielectric interface was characterized by high resolution scanning transmission electron microscopy. An increased roughness of 2–3 monolayers at the GaN surface was observed after blanket etching, which was correlated with the higher density of interface traps. The results presented in this paper give fundamental insight on how the etch and trench processing affects the trapping and robustness of trench-gate GaN-metal-oxide-semiconductor field effect transistors and provide guidance for the optimization of device performance.

This work investigates p⁺n⁻n GaN-on-Si vertical structures, through dedicated measurements and TCAD simulations, with the ultimate goal of identifying possible strategies for leakage and breakdown optimization. First, the dominant leakage processes were identified through temperature-dependent current–voltage characterization. Second, the breakdown voltage of the diodes was modelled through TCAD simulations based on the incomplete ionization of Mg in the p⁺ GaN layer. Finally, the developed simulation model was utilized to estimate the impact of varying the p-doping concentration on the design of breakdown voltage; while high p-doped structures are limited by the critical electric field at the interface, low p-doping designs need to contend with possible depletion of the entire p-GaN region and the consequent punch-through. A trade-off on the value of p-doping therefore exists to optimize the breakdown.