This letter experimentally demonstrates 1.2 kV normally-off p-GaN gate lateral high-electron-mobility transistors (HEMTs) on 200 mm diameter engineered substrates. The fabricated p-GaN gate HEMT with optimum gate-drain spacing exhibits a threshold voltage (V _th ) of 3.2 V, an ON/OFF ratio of 10 ⁸ , low specific ON-resistance (R _on,sp ) of 5.8 mΩ-cm ² and hard breakdown voltage (V _bd ) at 1800 V. Optimized devices also show good wafer scale uniformity (σ R_on = 1.2%) for the evaluated electrical parameters and passed on-wafer high temperature gate bias (HTGB) and reverse bias stress tests without device failures.

The vertical Gallium Nitride-on-Silicon (GaN-on-Si) trench metal-oxide-semiconductor field effect transistor (MOSFET) is a promising architecture for the development of efficient GaN-based power transistors on foreign substrates for power conversion applications. This work presents an overview of recent case studies, to discuss the most relevant challenges related to the development of reliable vertical GaN-on-Si trench MOSFETs. The focus lies on strategies to identify and tackle the most relevant reliability issues. First, we describe leakage and doping considerations, which must be considered to design vertical GaN-on-Si stacks with high breakdown voltage. Next, we describe gate design techniques to improve breakdown performance, through variation of dielectric composition coupled with optimization of the trench structure. Finally, we describe how to identify and compare trapping effects with the help of pulsed techniques, combined with light-assisted de-trapping analyses, in order to assess the dynamic performance of the devices.

In this work, we demonstrate the epitaxial growth of a gallium-nitride (GaN) buffer structure qualified for 1200 V applications on 200 mm engineered poly-AlN substrates with hard breakdown >1200 V. The manufacturability of a 1200 V qualified buffer structure opens doors to high voltage GaN-based power applications such as in electric cars. Key to achieving the high breakdown voltage is careful engineering of the complex epitaxial material stack in combination with the use of 200 mm engineered poly-AlN substrates. The CMOS-fab friendly engineered poly-AlN substrates have a coefficient of thermal expansion (CTE) that closely matches the CTE of the GaN/AlGaN epitaxial layers, paving the way for a thicker buffer structure on large diameter substrates, while maintaining the mechanical strength of the substrates and reaching higher voltage operation.

We propose to use a bilayer insulator (2.5 nm Al₂O₃ + 35 nm SiO2) as an alternative to a conventional uni-layer Al₂O₃ (35 nm), for improving the performance and the reliability of GaN-on-Si semi vertical trench MOSFETs. This analysis has been performed on a test vehicle structure for module development, which has a limited OFF-state performance. We demonstrate that devices with the bilayer dielectric present superior reliability characteristics than those with the uni-layer, including: (i) gate leakage two-orders of magnitude lower; (ii) 11 V higher off-state drain breakdown voltage; and (iii) 18 V higher gate-source breakdown voltage. From Weibull slope extractions, the uni-layer shows an extrinsic failure, while the bilayer presents a wear-out mechanism. Extended reliability tests investigate the degradation process, and hot-spots are identified through electroluminescence microscopy. TCAD simulations, in good agreement with measurements, reflect electric field distribution near breakdown for gate and drain stresses, demonstrating a higher electric field during positive gate stress. Furthermore, DC capability of the bilayer and unilayer insulators are found to be comparable for same bias points. Finally, comparison of trapping processes through double pulsed and V_th transient methods confirms that the V_th shifts are similar, despite the additional interface present in the bilayer devices.

This work investigates p⁺n⁻n GaN-on-Si vertical structures, through dedicated measurements and TCAD simulations, with the ultimate goal of identifying possible strategies for leakage and breakdown optimization. First, the dominant leakage processes were identified through temperature-dependent current–voltage characterization. Second, the breakdown voltage of the diodes was modelled through TCAD simulations based on the incomplete ionization of Mg in the p⁺ GaN layer. Finally, the developed simulation model was utilized to estimate the impact of varying the p-doping concentration on the design of breakdown voltage; while high p-doped structures are limited by the critical electric field at the interface, low p-doping designs need to contend with possible depletion of the entire p-GaN region and the consequent punch-through. A trade-off on the value of p-doping therefore exists to optimize the breakdown.

To make vertical GaN-based trench gate MOSFET devices commercially manufacturable, 200 mm engineered substrates with a poly-AlN core are a good substrate choice. The poly-AlN core, matched in thermal expansion to GaN, allows to grow high-quality thick GaN layers. Up to 11 $\mu$ m-thick GaN stacks were grown crack-free, with excellent control over the wafer warp. Breakdown values of 900 V were reached for the vertical p/n-junction. Full device processing was completed in a CMOS-compatible pilot line without any wafer breakage, demonstrating the mechanical strength of these substrates. On module level, a new gate trench profile combining a smooth sidewall and round corners, is presented. While a smooth sidewall is important for the ON-state performance of the devices, the rounded corners are beneficial for the OFF-state operation. A semi-vertical test vehicle was used to demonstrate the ON-state of the fabricated power transistors. For devices with an effective gate width ( $\textit{W}_{\text{G,\text{ef}\text{f}}}\text{)}$ of 180 mm and an active area of 1.4 mm $^{\text{2}}$ , an ON-state resistance could be achieved of 8 m $\Omega\cdot \text{cm}^{\text{2}}$ . By scaling the source contact length down, the device footprint could be decreased further. It is shown that for devices with a $\textit{W}_{\text{G,\text{ef}\text{f}}}$ of 60 mm this value could be further improved with best performing devices showing a 6.2 m $\Omega\cdot\text{ cm}^{\text{2}}$ ON-state resistance.