This paper firstly reported the 1200V enhancement-mode (E-mode) Gallium Nitride (GaN) based monolithic halfbridge (HB) integration platform on Sapphire substrate with ultra-thin buffer layer. Thanks to the specially designed ultra-thin un-doped buffer on Sapphire substrate, the shallow trench between high-side devices and low-side devices achieves over 3000V isolation without crosstalk and substrate biasing effects. Meanwhile, the breakdown voltage (BV) of high voltage (HV) p-GaN gate high electron mobility transistor (p-GaN HEMT) reaches 2300V, the normalized BV is 140% of GaN-on-SOI device. Low off-state drain leakage current is also achieved (~0.1μA/mm@1200V@175℃) due to the isolated substrate and thin buffer. Other electrical characteristics up to 175℃ of HV and low voltage devices are also evaluated. The excellent high temperature performances demonstrate the tolerance of the integration platform to low thermal conductance of Sapphire. Finally, the HV monolithic HB circuits are demonstrated to work under 800V-switching conditions at 175℃ by a boost converter.

This letter introduces a new physics-based SPICE modeling method for the dynamic on -state resistance ( R _on,dy ) of gallium nitride based p-type gate power high electron mobility transistors (p-GaN HEMTs). To describe the continuous variations of R _on,dy , a time-resolved electron mobility variation (Δ μ _eff ) model is proposed. Physical parameters including activation energy and voltage acceleration factor of traps in p-GaN HEMTs are extracted as the model parameters. Then, to achieve the goal of simulating R _on,dy , the proposed Δ μ _eff model is incorporated into the surface potential based advanced SPICE model for GaN HEMT. Simulative results prove the proposed models can predict the R _on,dy induced power loss.

This letter proposes a monolithically integrated bidirectional gate electrostatic discharge protection scheme for p-GaN power high-electron-mobility transistors (HEMTs), in which a dual-gate HEMT is designed as the discharging transistor. With this protection scheme, the forward/reverse transmission line pulsing failure current is enhanced from 0.156 A/0.08 A to 1.36 A/5.26 A, almost without sacrificing performances of the p-GaN power HEMT. Thanks to the bidirectional switching characteristics of the dual-gate device by sharing the drift region, only one discharging transistor is required in the scheme; as a result, the area of this protection scheme can be effectively saved by 40.8% compared to state-of-the-art scheme with the same protection capability.

This article proposes an aging reliability compact model with high accuracy to simulate trap effects after long-term aging in power Gallium Nitride (GaN) based high electron mobility transistors (HEMTs). Dynamic on-state resistance (Ron,dy) caused by trap effects is taken as an example to deliver the aging reliability modeling concepts and flows. Based on the mechanism of trap effects and accelerated-stress experiments, the variation model of electron mobility has been established, so that the degradation of Ron,dy after aging can be predicted. The structure of the advanced SPICE model for GaN HEMT (ASM-HEMT) is modified to integrate the mobility variation model into SPICE for convenient usage. In addition, the accuracy of the proposed model has been verified, and the RMSE value between measured data and simulated data under long-term high temperature reverse bias stress conditions is only 1.68%, thus the hazard of the power system caused by traps can be discovered and avoided in advance.

The degradations of electrical parameters for depletion mode GaN devices in the cascode configuration under repetitive hard-switching stress are investigated in detail. With the help of TCAD simulations and comprehensive experimental analysis, two different mechanisms behind the degradations are demonstrated. Under a relatively low V _ds hard-switching condition, hot electron injection is proved to be the only influence factor, which results in the increase of R _dson under low gate bias voltage. Furthermore, under the low V _ds switching condition, influence of different stages on the degradation trend of the device is verified. It is found that the turn- on procedure has a greater degradation risk due to higher energy consumption. However, when V _ds is high during hard-switching, the surface trapping effect is triggered due to high electric field at the end of gate field plate, and finally leads to the device degradation trend. It results in the increase of the R _dson under high gate bias condition. Therefore, considering the stability and safety of power systems, which adopt cascode devices as switches, shorter turn- on time or a soft-switching operation condition should be considered in the design.