Compared with the tremendous advancements of digital IC design automation over the last few decades, analog IC layout is still heavily manual, which is very tedious and error-prone. This is partially due to the sensitive layout dependent effects, but most important of all, the lack of readily available tools to designers. In this work, we present MAGICAL, an open-sourced, fully-automated analog IC layout system. MAGICAL is capable of handling system-level designs and generates GDSII format layout from unannotated netlists. We also introduce the various extensions that build on top of the original MAGICAL framework, successfully incorporating machine learning techniques for efficient, performance-driven analog layout synthesis. We hope that our works could contribute to the open-source EDA community and promote research in developing novel algorithms and methods for analog design automation.

MAGICAL is an open-source system for analog and mixed-signal (AMS) circuit layout synthesis. Using custom place-and-route and constraint extraction algorithms, MAGICAL provides a fully-automated layout implementation flow. MAGICAL 1.0 has been proven in silicon with a 40-nm 1GS/sΔΣ ADC. The source code has been released to enable broad usage. Recently, MAGICAL has also been extended to cover more circuit classes such as SAR-ADC. This tutorial/perspective paper describes the overall MAGICAL framework and algorithms. We also provide a tutorial on how to use and extend MAGICAL and discuss future research directions for AMS layout design automation.

This paper presents an end-to-end successive-approximation-register (SAR) analog-to-digital converter (ADC) compiler that generates design solutions from top-level specification to GDSII layout with a short turnaround time of 5 hours. Two prototype SAR ADCs operating at 1MS/s and 80MS/s are compiled in 40nm CMOS. Measurement results demonstrate a wide conversion range, presenting both analog and technology-limited performances. The compiler requires minimum manual involvement and can significantly boost design efficiency for performance retargeting, technology migrations, and agile development of IP blocks.

Placement is a critical step in layout automation for analog and mixed-signal (AMS) integrated circuits (IC). It determines the proximity of devices and influences the wiring topology, significantly impacting post-routing parasitics and coupling capacitance. Existing analog placement techniques mainly focus on geometric constraints in analog building blocks. However, there yet lacks an effective way to consider the system-level signal flow for sensitive AMS circuits. Leveraging prior knowledge from schematics, we propose considering the critical signal paths in automatic AMS placement. A multilevel analog layout automation flow is further developed to reduce manual efforts in synthesizing hierarchical AMS circuits. Experimental results demonstrate the efficiency and effectiveness of our proposed framework with a 22.8% reduction in routed wirelength compared to state-of-theart AMS placer and a 10 dB improvement in the signal-to-noiseand-distortion ratio (SNDR) for an ADC.

Recent advances in analog device sizing algorithms show promising results on the automatic schematic design. However, the majority of the sizing algorithms are based on schematic-level simulations and layout-agnostic. The physical layout implementation brings extra parasitics to the analog circuits, leading to discrepancies between schematic and post-layout performance. This performance gap raises questions about the effectiveness of automatic analog device sizing tools. Prior work has leveraged procedural layout generation to account for layout-induced parasitics in the sizing process. However, the need for layout templates makes such methodology limited in application. In this paper, we propose to bridge automatic analog sizing with post-layout performance using state-of-the-art optimization-based analog layout generators. A quantitative study is conducted to measure the impact of layout awareness in state-of-the-art device sizing algorithms. Furthermore, we present our perspectives on the future directions in layout-aware analog circuit schematic design.