This paper describes a short-reach serial link to connect chips mounted on the same package or on neighboring packages on a printed circuit board (PCB). The link employs an energy-efficient, single-ended ground-referenced signaling scheme. Implemented in 16-nm FinFET CMOS technology, the link operates at a data rate of 25 Gb/s/pin with 1.17-pJ/bit energy efficiency and uses a simple but robust matched-delay clock forwarding scheme that cancels most sources of jitter. The modest frequency-dependent attenuation of short-reach links is compensated using an analog equalizer in the transmitter. The receiver includes active-inductor peaking in the input amplifier to improve overall receiver frequency response. The link employs a novel power supply regulation scheme at both ends that uses a PLL ring-oscillator supply voltage as a reference to flatten circuit speed and reduce power consumption variation across PVT. The link can be calibrated once at an arbitrary voltage and temperature, then track VT variation without the need for periodic re-calibration. The link operates over a 10-mm-long on-package channel with -4 dB of attenuation with 0.77-UI eye opening at bit-error rate (BER) of 10⁻¹⁵. A package-to-package link with 54 mm of PCB and 26 mm of on-package trace with -8.5 dB of loss at Nyquist operates with 0.42 UI of eye opening at BER of 10⁻¹⁵. Overall link die area is 686 μm x 565 μm with the transceiver circuitry taking up 20% of the area. The transceiver's on-chip regulator is supplied from an off-chip 950-mV supply, while the support logic operates on a separate 850-mV supply.

This article presents a clock-forwarded, inverter-based short-reach simultaneous bi-directional (ISR-SBD) physical layer (PHY) targeted for die-to-die communication over silicon interposers or similar high-density interconnect. Short-reach links of this type are increasingly important to support larger systems built with chiplets and multiple die and to facilitate the shift to medium- and long-range optical communication based on silicon photonics. This project explores the advantages of simultaneous bi-directional signaling (SBD) over other bandwidth-doubling techniques (e.g., PAM4). Fabricated in a 5-nm standard CMOS process, the ISR-SBD PHY demonstrates 50.4 Gb/s/wire (25.2 Gb/s each direction) and 0.297 pJ/bit on a 750-mV supply over a 1.2-mm on- chip channel.

This article presents an inverter-based short-reach ac-coupled toggle (ISR-ACT) link targeted for short-reach die-to-die communication over silicon interposer or similar high-density interconnect. The ISR-ACT’s transmitter (TX) sends non-return-to-zero (NRZ) data through a small series capacitor to inject low-swing pulses into the line. These pulses are amplified and latched by a two-stage receiver (RX), where the 1st-stage transimpedance amplifier (TIA) amplifies the pulse data and positive feedback around both stages captures the data and maintains the dc level on the line. Achieving low signal swing through a capacitor divider, the ACT driver consumes less than half the power compared to regular rail-to-rail CMOS drivers while providing dc voltage isolation between the driver and the RX. Fabricated in a 5-nm standard CMOS process, the ISR-ACT link, operating on a 0.75-V supply, shows 0.66 UI margin at 25.2 Gb/s/wire over a 1.2-mm on-chip channel and demonstrates an energy efficiency of 0.190 pJ/bit.

Availability of a reliable ON-chip oscillator can secure a system-on-chip (SoC) against physical clock attacks by enabling applications such as boot-up using ON-chip oscillator and hardware clock monitors. This article proposes a frequency-error feedback (FEF) loop-based relaxation oscillator for such applications. It suppresses the low-frequency noise and improves the time interval error (TIE) without degrading the period jitter. It also stabilizes the oscillator against supply and temperature variations. A 77-MHz oscillator prototype is fabricated in a commercial 5-nm FinFET process. Operating from 0.9-V digital and 1.2-V analog supplies, the prototype consumes a total of 0.84 mW and occupies an area of 0.0152 mm2. It achieves a TIE of 3 ns over 10 K cycles which is 3 $\times$ better than an oscillator without an FEF loop. Chip samples are picked from four wafer split lots. The worst case frequency variation measured from 16 samples is $\pm0.25\%$ across an analog supply change of 1.1–1.35 V, while a variation of $\pm 0.3\%$ is measured over $-$ 40 to 125 $^\circ$ C temperature from eight samples.

Due to the increasingly complex design rules and geo-metric layout constraints within advanced FinFET nodes, automated placement of full-custom analog/mixed-signal (AMS) designs has become increasingly challenging. Compared with traditional planar nodes, AMS circuit layout is dramatically different for FinFET technologies due to strict design rules and grid-based restrictions for both placement and routing. This limits previous analog placement approaches in effectively handling all of the new constraints while adhering to the new layout style. Additionally, limited work has demonstrated effective routability modeling, which is crucial for successful routing. This paper presents a robust analog placement framework using satisfiability modulo theories (SMT) for efficient constraint handling and routability modeling. Experimental results based on industrial designs show the effectiveness of the proposed framework in optimizing placement metrics while satisfying the specified constraints.