A chiplet is an integrated circuit (IC) that encompasses a well-defined subset of an overall systems functionality. In contrast to traditional monolithic system-on-chips (SoCs), chipletbased architecture can reduce costs and increase reusability, representing a promising avenue for continuing Moore’s Law. Despite the advantages of multi-chiplet architectures, floorplan design in a chiplet-based architecture has received limited attention. Conflicts between cost and performance necessitate a trade-off in chiplet floorplan design since additional latency introduced by advanced packaging can decrease performance. Consequently, balancing performance, cost, area, and reliability is of paramount importance. To address this challenge, we propose Floorplet (Floorplan chiplet), a framework comprising simulation tools for performance reporting and comprehensive models for cost and reliability optimization. Our framework employs the open-source Gem5 simulator to establish the relationship between performance and floorplan for the first time, guiding the floorplan optimization of multi-chiplet architecture. The experimental results show that our method decreases inter-chiplet communication costs by 24.81%.

Interposer-based packaging has gained tremendous popularity in integrating advanced logic and memory chiplets for artificial intelligence and high-performance computing systems. The size of the silicon interposer is the critical bottleneck in improving the performance of integrated systems by mounting more and more advanced chiplets, such as high bandwidth memory (HBM). Nowadays, ultra large wafer scale integration is a popular alternative to integrate large amounts of advanced chiplets on a big wafer scale silicon interposer. However, wafer scale silicon interposers cannot be manufactured by one mask due to the reticle limitation. Therefore, the mask stitching technique is used to manufacture ultra large systems by applying multiple masks for different sub-regions of an ultra large silicon interposer. To achieve the alignment of two adjacent sub-regions manufactured by different masks, the two sub-regions have an overlapped stitching region. Previous algorithms cannot handle the special design rules of mask stitching regions and are not efficient enough to generate high-quality routing solutions. In this work, we propose a fast routing algorithm for mask stitching regions to efficiently solve the special design rules. The time complexity of the proposed algorithm is O(n log n), where n is the number of nets. Compared with state-of-the-art work, our algorithm can achieve 100% routability with an effective reduction of wirelength. Furthermore, the proposed algorithm can achieve a speedup of thousands of times.

In modern advanced fan-out wafer-level packaging (FOWLP), redistribution layers (RDLs) are used to implement efficient interconnections among chips, where both flexible vias and irregular pad structures can be deployed to realize highly integrated heterogeneous systems. With the sharp increase in chip densities, however, it becomes challenging to fully utilize the routing resources in RDLs. The routing graph without optimized resource planning can lead to significant deterioration in the solution quality of RDL design. Furthermore, prior work determines via locations in the RDLs before identifying wire routes, thus offsetting the advantages of flexible vias and irregular pads. To systematically solve the RDL routing problem in FOWLP, in this article, we propose a hierarchical partitioning-based interchip routing method considering both flexible vias and irregular pads, so that optimized RDL solutions can be generated automatically and efficiently. The proposed method includes the following key techniques: 1) a channel planning method for optimized routing region partition and a dynamic routing graph-based pathfinding method for efficient global routing; 2) a binary-search-based hierarchical tile segmentation method for conflict removal and wirelength reduction; 3) a novel monotonicity-analysis-based access point optimization method and a staggered via planning strategy for both wirelength and detour reduction; and 4) a geometry-based detailed routing algorithm for innertile wire routing. The experimental results demonstrate that the proposed algorithm leads to 100% routablility and 4.8% wirelength reduction on average compared to the state-of-the-art work, with a maximum reduction rate of 10.3% across all the benchmarks.

2.5D packaging has become a popular alternative to integrate advanced logic and memory chiplets for high-performance computing and artificial intelligence systems. In the conventional design flow, chiplets and packages are independently designed and then integrated at the assembly stage. To bridge the gap between chiplet designs and package designs, existing chiplet-package co-design methods iteratively optimize chiplet layouts to improve the performance of the entire system. However, Redistribution Layer (RDL) routing, which finishes the interconnections between chiplets at the package level and significantly affects the system performance, is neglected in the existing co-design flows. Therefore, this article proposes an effective chiplet-package co-design flow focusing on the RDL routing to optimize the package system performance dynamically. The proposed co-design flow can fill in the missing link, package-level co-optimization, of previous design flows. In the proposed co-design flow, we propose an efficient RDL routing algorithm to iteratively optimize the substrate layout based on the cross-boundary timing context extracted from both chiplets and the package. The proposed RDL routing algorithm has two critical techniques, including (1) a Maximal Independent Set-based (MIS-based) pin assignment method to dynamically optimize the pin positions of nets and (2) a network-flow-based router to generate routing layouts. Experimental results show that the proposed design flow can gradually improve the maximum frequency of a real design to the target performance, 400 MHz.

Due to the rapid expansion of printed circuit board (PCB) designs, accompanied by diverse design rules and specific constraints, there has been a substantial increase in manual design engineering efforts. To address this challenge, industries are seeking productivity improvements through automated placement techniques. However, existing placers primarily target VLSI placement and do not align well with PCBs’ unique characteristics. This mismatch arises from both the customization of PCBs and the complexity of the problem, which involves considering various constraints such as priorities, irregularities, and alignment. This paper introduces HiePlace, an efficient mathematical programming (MP)-based placement framework designed explicitly for PCBs. It aims to address the diverse constraints and achieve better performance. To address the issue of time-consuming computation in the direct MP-based algorithm, we present two innovative acceleration techniques: (1) In the initial stage, we introduce a dynamic programming approach to prioritize the placement of core components. This technique effectively reduces the solution space and enhances the overall placement quality. (2) Additionally, we propose a relaxation algorithm to minimize the number of boolean variables and further narrow down the solution space. This approach enables more efficient placement results by considering the problems specific constraints. Experimental results show that the proposed framework produces 7.7× speed up and 66% cost reduction.