The Internet of Things (IoT) is an interface with the physical world that usually operates in random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips: power consumption, power supply, artificial intelligence (AI), small-signal acquisition, and evaluation criteria. To overcome these challenges, many works recently aimed at IoT system design have emerged. This work reviews the architecture and circuit innovations that have contributed to IoT developments. This paper does not cover security of IoT. Event-driven architectures and nonuniform sampling ADCs significantly reduce the long-term average power. Besides, embedding AI engines in IoT nodes (AIoT) is one critical trend. The computing-in-memory technique improves the energy efficiency of the AI engine. Asynchronous spike neural networks (ASNNs) AI engines show low power potential. In addition to data processing, small-signal acquisition is also critical. The charge-domain analog-front-end (AFE) techniques such as floating inverter-based amplifiers improve energy efficiency. In addition to the above low power and high energy efficiency technologies, energy harvesting can also enhance the lifetime of AIoT devices. This article discusses recent ambient RF and natural energy harvesting approaches and high-efficiency DC-DC with a wide load range. Finally, novel evaluation criteria are introduced to establish benchmark standards for AIoT chips.

This article presents a 148-nW always-on wake-up system that drastically reduces the system power consumption of Internet of Things (IoT) sensor nodes while oftentimes operating in random-sparse-event (RSE) scenarios. To significantly reduce the long-term average (LTA) power consumption and realize multiapplication and intelligent event detection, three techniques are proposed: 1) In a three-stage pipelined event-driven architecture, a frame generator and a convolutional neural network intelligent inference engine (CNN IIE) in stage III are event-driven by the preliminary detectors in stage II, and the detectors are triggered by a level-crossing (LC) analog-to-digital converter (ADC), i.e., stage I, dramatically reducing the overall power consumption. 2) The clock-free pulse-based instant rate of change (IROC) feature extractor directly processes the asynchronous pulses of the LC-ADC outputs in the temporal domain instead of utilizing a conventional power-hungry frequency-domain method. 3) A reconfigurable IROC, the frame generator, and the CNN IIE provide adaptive intelligence for various IoT events, enhancing the accuracy of multipurpose detection with ultralow power. We demonstrate two artificial intelligence IoT (AIoT) applications at 0.6-V V _DD . For electrocardiogram (ECG) recognition, one example works at a typical event rate (ER) of ~4800/h, with an active power of 1.68 $\mu \text{W}$ and a precision of up to 99%; the other is used for keyword spotting (KWS), where the chip achieves 378 nW at ~720/h ER and 94% accuracy. The LTA power is bounded to 148 nW, while the event-driven chip is on call and waiting for events; this chip dominates the AIoT device battery life in RSE scenarios.

This work presents an ultra-low-power software-defined always-on wake-up system to drastically decrease the system power of Internet of Things (IoTs) devices, which usually operate in random-sparse-event (RSE) scenarios. It mainly thanks to a clock-free time-shielding level-crossing ADC (TS-LCADC), software-defined clock-free multi-function detectors, and an asynchronous pipelined event-driven architecture. First, by quantifying RSE noisy signals with clock-free adaptive sampling in a signal-noise-rejecting manner, the proposed TS-LCADC reduces number of sampling points and power, and consumes only 41 nW when on-call waiting for IoT events. Second, the proposed clock-free multi-function detectors with offline and online programmability are able to character the signal features of versatile IoTs events and allow versatile and dynamic wake-up functions. Third, the proposed asynchronous pipelined event-driven architecture minimizes the system activity and thus power, because a power-hungry high-performance system (HPS) is only woken up when a detected parameter crosses its corresponding threshold. As such, the long-term average power (LTA-power) is dominated by the always-on circuits in RSE scenarios. The measurement results achieve 71–75 nW for three typical applications, i.e., heart rate, epilepsy, and keyword envelope detection. The LTA power is only 57 nW when waiting for RSE events, which is 30 $\times $ lower than a prior general-purpose wake-up chip. Compared with other works of dedicated voice and acoustic wake-up functions, this work consumes 2 $\times $ and 17 $\times $ less power, respectively, while featuring 16 $\times $ higher signal bandwidth and a broader versatility.

This article presents a clock-free spiking neural network (SNN) intelligent inference engine (IIE) for artificial intelligence of things (AIoT) sensor nodes, which often operate in random-sparse-event (RSE) scenarios. The IIE drastically reduces the system’s long-term average (LTA) power consumption, improves energy efficiency, and achieves microsecond level inference latency. Three techniques are proposed: 1) A clock-free SNN architecture without clock tree, frame generator, and arbiter, is driven by the output spikes, which are encoded with level-crossing (LC) sampling method; the circuit activity is completely related to event activity and spike rates, dramatically reducing the overall power consumption and latency. 2) The bioinspired leaky-integrate-fire (LIF) neurons directly extract the time-domain information from asynchronous spikes, reducing the network size and number of operations. 3) The computing-in-memory (CIM) and mixed-signal synapse-neuron circuits are employed to increase the SNN parallelism and avoid weight movements, thus improving the energy efficiency and response speed. The measured LTA power is bounded at 82 nW while the event-driven chip is on call and waiting for events; the energy efficiency is 0.53 pJ per synapse operation (SOP), only 1/3 that of state-of-the-art methods at 4bit weights even with 180 nm technology. We demonstrate electrocardiogram (ECG) recognition as a typical AIoT application, and the power consumption is less than 350 nW. The measured accuracy of abnormal ECG detection is 90.5%. Moreover, the latency is only 40 $\mu $ s to realize real-time NN inference. This work provides an effective solution for AIoT nodes that require both ultralow power and fast response.

Tunnel FET is recognized as one of the most promising candidates for ultra-low power applications due to its ultra-low off current and CMOS compatibility. However, some characteristics of TFET caused by asymmetric device structure and special conduction mechanism may make conventional topologies of logic circuits no longer applicable. Our previous work has reported that TFET stacking will result in severe current degradation, which makes traditional logic cells not applicable. In this paper, two solutions are proposed: first, from a logic cell perspective, novel hybrid TFET-MOSFET topologies of standard logic cells are proposed, which achieve more than 2 times lower hardware cost and intrinsic delay, hence up to 4 times lower area-power-delay product (APDP) than that of conventional TFET logic circuits. Compared to MOSFET logic circuits, the designs achieve almost 2 orders of magnitude lower power and up to 34 times lower APDP. Second, from a large-scale circuit perspective, an optimized digital front-end (DFE) is proposed. Taking serial peripheral interface (SPI) as an example, SPI circuit using the optimized DFE achieves 46% lower delay and 4 times lower APDP than that of traditional TFET SPI, and 3 orders of magnitude lower static power and APDP than that of MOSFET SPI.

Lithium metal batteries (LMBs), the energy conversion and storage technologies that have been thoroughly investigated, are utilized in various areas. Most current commercial LMBs use liquid electrolytes, but their safety cannot be guaranteed. In contrast, all-solid-state LMBs with solid-state electrolytes (SSEs) are regarded as next-generation energy storage systems owing to their enhanced safety. In the examination of SSEs, the benefits of composite SSEs (CSSEs) are particularly prominent. CSSEs relying on multiphase composites have better flexibility to tailor electrolyte performance based on demand and, thus, the design of components. Based on existing research presentations, we herein review the development of CSSEs. Firstly, the essential components of CSSEs are introduced, focusing on explaining the transport channel of Li ions within the polymer matrix and the impact of various fillers on this channel. The key performance parameters of CSSEs are described in detail. Subsequently, the fillers in CSSEs are meticulously classified; the critical roles played by different fillers in the polymer matrix are clarified, and the hotspots of current research are summarized. Furthermore, the prevalent structural design methodologies in CSSEs are examined, and the impact of various structures on battery performance is elucidated. Finally, the current problems of CSSEs and the future development prospects are summarized. This review is significant because it provides ideas for the design of CSSEs and contributes to the development of all-solid-state LMBs to realize their wide application.