20 June 2025 in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Unstructured pruning introduces significant sparsity in deep neural networks (DNNs), enhancing accelerator hardware efficiency. However, three critical challenges constrain performance gains: 1) complex fetching logic for nonzero (NZ) data pairs; 2) load imbalance across processing elements (PEs); and 3) PE stalls from write-back contention. This brief proposes an energy-efficient accelerator addressing these inefficiencies through three innovations. First, we propose a Cartesian-product output-row-stationary (CPORS) dataflow that inherently matches NZ data pairs by sequentially fetching compressed data. Second, a multilevel partial sum reduction (MLPR) strategy minimizes write-back traffic and converts random PE stalls into manageable load imbalance. Third, a kernel sorting and load scheduling (KSLS) mechanism resolves PE idle/stall and achieves PE array-level load balancing, attaining 76.6% average PE utilization across all sparsity levels. Implemented in 22-nmCMOS, the accelerator delivers $1.85\times $ speedup and $1.4\times $ energy efficiency over baseline and achieves 25.8 TOPS/W peak energy efficiency at 90% sparsity.
25 December 2025 in IEICE Electronics Express
Deep neural networks (DNNs) have achieved remarkable success in critical domains such as computer vision. However, their substantial model scale and computational demands hinder deployment on resource-constrained edge devices. Bit-serial accelerators (BSAs) leverage significant bit-level sparsity (BLS) in weights and activations to accelerate inference. Unstructured BLS causes hardware inefficiency, while existing static pruning methods cannot adapt to real-time activations. To address these challenges, we propose BitFleX, a BSA enabling runtime semi-structured pruning for both weights and activations. Specifically, we introduce Bit-Term Decomposition (BTD) encoding to enhance inherent BLS and reduce pruning complexity. Additionally, a pruning-error predictor dynamically selects operands for sparsification with minimal error. Experiments show BitFleX achieves 87.5% BLS in ViT-B with <1% Top-1 accuracy loss on ImageNet, yielding 5.86× speedup over baseline and 23.61 TOPS/W peak energy efficiency.