When VLSI technology scales down to sub-40nm process node, systematic variation introduced by the lithography is a persistent challenge to the manufacturability. The limitation of the resolution enhancement technologies (RETs) forces people to adopt a regular cell design methodology. In this paper, targeted on 1D cell design, we use simulation data to analyze the relationship between the line-end gap distribution and printability. Based on the gap distribution preferences, an optimal algorithm is provided to efficiently extend the line ends and insert dummies, which will significantly improve the gap distribution and help printability. Experimental results on 45nm and 32nm processes show that significant improvement can be obtained on edge placement error (EPE).

Non-integer multiple cell height (NIMCH) standard-cell libraries offer promising co-optimization for power, performance and area in advanced technology nodes. However, such non-uniform design introduces new layout constraints where any sub-region can only accommodate gates of the same cell height due to manufacturability concerns. The existing physical design flow for NIMCH circuits, which handles the layout constraint by clustering and relocating gates according to their cell heights, often leads to substantial gate displacement that harms circuit performance. To alleviate the above issue, this paper proposes a row-based logic resynthesis procedure that explicitly adjusts cell heights after initial placement without changing cell positions. Experiment results demonstrate that compared with the conventional NIMCH physical design flow, our proposed approach can reduce the maximal delay by 26.1%.

In modern advanced fan-out wafer-level packaging (FOWLP), redistribution layers (RDLs) are used to implement efficient interconnections among chips, where both flexible vias and irregular pad structures can be deployed to realize highly integrated heterogeneous systems. With the sharp increase in chip densities, however, it becomes challenging to fully utilize the routing resources in RDLs. The routing graph without optimized resource planning can lead to significant deterioration in the solution quality of RDL design. Furthermore, prior work determines via locations in the RDLs before identifying wire routes, thus offsetting the advantages of flexible vias and irregular pads. To systematically solve the RDL routing problem in FOWLP, in this article, we propose a hierarchical partitioning-based interchip routing method considering both flexible vias and irregular pads, so that optimized RDL solutions can be generated automatically and efficiently. The proposed method includes the following key techniques: 1) a channel planning method for optimized routing region partition and a dynamic routing graph-based pathfinding method for efficient global routing; 2) a binary-search-based hierarchical tile segmentation method for conflict removal and wirelength reduction; 3) a novel monotonicity-analysis-based access point optimization method and a staggered via planning strategy for both wirelength and detour reduction; and 4) a geometry-based detailed routing algorithm for innertile wire routing. The experimental results demonstrate that the proposed algorithm leads to 100% routablility and 4.8% wirelength reduction on average compared to the state-of-the-art work, with a maximum reduction rate of 10.3% across all the benchmarks.

Recently, the challenge of integrating an increasing number of transistors on a single die to adhere to Moores Law has spurred the need for innovative packaging solutions. Power/ground planes are integral to packages, and designers typically strive to maximize their size. This provides shielding and maintains constant impedance for adjacent high-speed signal wires, benefiting signal integrity. Additionally, large power/-ground planes help reduce DC IR drops, enhancing power integrity. However, the necessity for multiple power/ground nets, each requiring independent power/ground planes within a package, makes the optimal allocation of limited free space a complex task. This paper introduces a game-theoretic optimization method aimed at evenly mitigating DC IR drops across the multi-layer package power/ground planes. In the formulated game of achieving the ideal power/ground plane design, we can enhance the use of package space and realize a design with evenly distributed DC IR drops across all power/ground planes. This is accomplished by adjusting strategies and reaching a state of Nash equilibrium in the allocation of free space. Additionally, we propose a rapid multi-layer power/ground plane DC IR drop evaluation and a power/ground plane legalization method to bolster our optimization method.

Non-integer multiple cell height (NIMCH) libraries have been adopted by advanced manufacturers in the latest technology node, to offer better power efficiency, performance optimization, and area occupancy. However, in order to meet manufacturing requirements, such as power supply, NIMCH placement must comply with several additional layout restrictions. Currently, the state-of-the-art method applies resynthesis and legalization to the initial placement result to achieve a minimum displacement. However, the two decoupled phases lead to a reduction in the solution space and an insensitivity to timing. Therefore, we propose an iterative algorithm with corresponding data structure, which comprehensively considers displacement and timing information. Experiments demonstrate that our method can generate legalized NIMCH designs with a lower maximum delay and a reduced area.