The dynamic on-resistance ( r _ON ) of two mainstream 600 V/650 V p -GaN gate power high-electron-mobility transistors (HEMTs) with Ohmic- and Schottky-type p -GaN gate contacts are characterized under the hard-switching condition and show strong dependences on the gate driving conditions under both double-pulse and multipulse testing modes. The statistical measurement of multiple samples indicates this is a representative phenomenon in these two types of commercial p -GaN gate power HEMTs. For Ohmic-type p -GaN gate HEMT, gate injection current ( I _G ) at the on state from the p -GaN gate facilitates a faster detrapping process and contributes to a smaller dynamic r _ON . For Schottky-type p -GaN gate HEMT, the dynamic r _ON shows a strong dependence on the gate overdrive voltage ( V _GS ) because the higher V _GS can compensate the increase in dynamic r _ON induced by the positively shifted V _TH under high drain bias. A larger I _G (from 1.2 to 22 mA) and higher V _GS (from 5 to 7 V) play the most important role in suppressing the dynamic r _ON under high switching frequency and high drain bias condition (i.e., 400 kHz/400 V), where the reduction of dynamic r _ON is 13.6% and 17.1% for Ohmic-type and Schottky-type p -GaN gate HEMTs, respectively.

With a switching drain bias, the gate reliability of Schottky-type ${p}$ -GaN gate high-electron-mobility transistors (HEMTs) under AC positive gate bias stress has been systematically investigated. The mean-time-to-failure (MTTF) under such application-relevant stress is found to be prolonged compared to that extracted from static and AC gate bias stress tests with the absence of a switching drain bias and exhibits positive coefficients with frequency and OFF-state drain bias ( ${V} _{\text {DSQ}}$ ). Such results can be explained by the drain-induced hole insufficiency in the gate stack at large ${V} _{\text {DSQ}}$ , a physical mechanism that results in elevated energy band at ON-state when ${V} _{\text {DSQ}}$ is just switched to low voltage. This non-equilibrium transient status could suppress injection of electrons from the 2DEG channel to the ${p}$ -GaN gate, which in turn substantially weakens the hot-electron’s generation in the depleted ${p}$ -GaN layer and the subsequent bombardment to the gate-metal/ ${p}$ -GaN interface, and thus prolongs the gate lifetime.

The dynamics of the intrinsic threshold voltage ( ${V}_{{\text {TH}}}{)}$ shift in 650-V Schottky-type p-GaN gate HEMT under high-frequency switching is investigated by a bootstrap voltage clamping circuit in which the GaN HEMT serves as the key bootstrapping device. This new testing setup covers a wide range of OFF-state drain bias ( ${V}_{{\text {DSQ}}}{)}$ up to 400V, a short OFF-to-ON (or stress-to-sense) delay ( ${T}_{{\text {delay}}}{)}$ of 60ns, and a high switching frequency ( ${f}_{{\text {sw}}}{)}$ up to 2MHz. The dynamic ${V}_{{\text {TH}}}$ ’s dependences on ${V}_{{\text {DSQ}}}$ and ${f}_{{\text {sw}}}$ are characterized by this testing setup. A higher V _DSQ (up to 400V) results in a larger dynamic ${V}_{{\text {TH}}}$ shift ( $\Delta {V}_{{\text {TH}}}{)}$ . The $\Delta {V}_{{\text {TH}}}$ exhibits a gradually increasing trend under the continuous high-frequency switching mode. In addition, after continuous switching operation for $200\mu \text{s}$ , the maximum $\Delta {V}_{{\text {TH}}}$ shows no ${f}_{{\text {sw}}}$ dependence with a wide range of frequency from 50kHz to 2MHz.

A 650-V/84-mΩ normally- off GaN/SiC cascode device is demonstrated with systematic static and dynamic characterizations. The cascode device features a low-voltage enhancement-mode (E-mode) gallium nitride (GaN) high electron mobility transistor (HEMT) to enable normally- off gate control, and a 650-V normally- on silicon carbide (SiC) JFET provides the high-voltage blocking capability. The GaN/SiC cascode device exhibits many application-desired behaviors, including reverse conduction capability, avalanche breakdown capability, thermally stable threshold voltage, low input/output capacitances, no dynamic R _ON degradation, and negligible dynamic V _TH shift. In addition, a customized double-pulse test board is built to evaluate the switching performance of this cascode device and other 650-V SiC-based power devices. This cascode device adopting low-voltage GaN HEMT has low Q _G × R _ON and exhibits excellent switching performance. The switching losses ( E _ON and E _OFF ) are much smaller than that of the 650-V Si/SiC cascode device and comparable to that of the state-of-the-art 650-V SiC MOSFETs.

Although the gallium nitride (GaN) high-electron-mobility transistor/silicon carbide (SiC) junction field-effect transistor (JFET) cascode device exhibits certain performance advantages over the SiC metal–oxide–semiconductor field-effect transistor (MOSFET), its robustness in harsh operating conditions is unknown. In this work, the short-circuit (SC) robustness of 650-V GaN/SiC cascode devices is characterized, analyzed, and compared with that of several mainstream SiC MOSFETs. GaN/SiC cascode devices exhibit competitive SC capability. Different failure modes are observed: thermal runaway in the SiC JFET of the cascode device and gate-to-source breakdown in the SiC MOSFET. The difference is associated with the configuration of the dielectric above SiC in the JFET and the source pad layout. According to the waveforms in SC events, failure spots, and thermal simulation results, a thermal runaway in the SiC JFET is attributed to the positive feedback between the drain leakage current and the junction temperature in the local area (hotspot) without the source pad on the top. The SC withstand time of the cascode device can be extended by reduction of the active area without the source pad.

The short circuit (SC) behavior of a newly developed GaN-HEMT/SiC-JFET cascode device is investigated in this work. The reverse leakage current through the drain-side PN junction (I _R ) of the SiC JFET under SC conditions is measured simultaneously during the SC event. I _R of the SiC JFET increases to 6.4 A at the end of a 5-μs nondestructive SC pulse. The increase of I _R during the SC pulse induces a turning point in the SC current waveform and a dramatic negative threshold voltage shift (>30 V) in the SiC JEFT, resulting in high transient drain-to-source voltage in the GaN HEMT. The underlying mechanism is associated with the increase of local potential in the P-type layer of the SiC JFET with inevitable spread resistance (R _SPD ). It is suggested that reducing R _SPD can improve SC capability and high I _R should be considered in SC failure mechanism analysis and the design of external gate resistance of the SiC JFET.