In this work, we comprehensively studied the stress in gate-all-around (GAA) transistor and beyond, focusing on the S/D geometry. Lattice kinetic Monte Carlo (LKMC) simulation model was first used to investigate the realistic growth of source/drain (S/D) epitaxy and its impact on the channel stress, validating the accuracy of stress trends from continuum S/D epitaxy simulations. Furthermore, this study reveals that the compressive stress in the pFET channel can be significantly boosted by up to 56.1% with the gate extension length (L_EXT) reducing from 8 to 0 nm. Meanwhile, the tensile stress in the nFET channel remains nearly zero and similar for different L_EXT. Other important GAA structural innovations were also carefully studied. While the full bottom dielectric isolation (BDI) detrimentally degrades the channel stress, the under-gate BDI effectively recovers it (0.12 to -2.57 GPa) fortunately. For stress impact by the self-aligned backside contact (SABC), The Si_0.7Ge_0.3 placeholder can further enhance the compressive stress in the pFET channel, elevating it to -2.69 GPa, but slightly compromises the nFET for the tensile stress. For SABC schemes, the channel stress without BDI is similar to that with BDI. This detailed study of channel stress in nanosheet field-effect transistor (NSFET) provides new insights for the development of next-gen logic nodes.

Flip FET (FFET), a novel self-aligned stacked transistor architecture with dual-sided transistor stacking, was recently proposed and demonstrated. However, due to the vertically stacking nature, the electrical coupling of frontside (FS) and backside (BS) transistors should be carefully examined. Here, we thoroughly investigated the coupling effects of FFET at both device and circuit levels using TCAD simulation. For the device level assessment, the coupling effects are measured by the threshold voltage (V_th) shift and the subthreshold swing (SS) degradation of transistors, as a result of the bias applied on the other side’s transistors. At the circuit level, the propagation delay of FFET inverters was studied. In the worst case scenario, the V_th shift is up to 135 mV, the SS degradation up to 235 mV/dec (from 72.6 mV/dec), and the inverter’s delay change up to 4.41% is found, which is undesired and intolerable for circuit designs. To address this issue, a novel middle dielectric isolation (MDI) technique was proposed and found to be quite effective in blocking the electrical field from the other side, thus reducing the coupling effects. By implementing the MDI technique, the V_th shift of no more than 0.85 mV, negligible SS degradation, and the INV’s delay change of less than 0.6% are realized. We also investigated MDI FFET’s gate structure innovations e.g., Pi-gate, omega-gate (OG), and gate-all-around (GAA) to enhance the gate control, by which the V_th shift can be minimized to 0.12 mV. This work paves the way for practical implementation of FFET in the future.

Recently, we proposed a novel transistor architecture for 3-D stacked FETs called Flip FET (FFET), featuring N/P transistors back-to-back stacked and dualsided interconnects. With dual-sided power rails and signal tracks, FFET can achieve an aggressive 2.5 T cell height. As a tradeoff, the complex structure and limited numbers of M0 tracks could limit the standard cell design. As a solution, multiple innovations were introduced and examined in this work. Based on an advanced node design rule, several unique building blocks in FFET such as drain merge (DM), gate merge (GM), field DM (FDM), and buried signal track (BST) were investigated. Other key design concepts of multi-row, split gate (SG), and dummy gate (DG) insertion were also carefully studied, delivering around 35.6% area reduction compared with 3 T CFET. Furthermore, the symmetric design of FFET has unique superiority over CFET thanks to the separate N/P logic on two sides of the wafer and their connections using DM and GM. New routing scheme with dual-sided output pins on both wafer frontside (FS) and backside (BS) was proposed for the first time. Finally, we conducted a comprehensive evaluation on complex cell design, taking AOI22 as an example. New strategies were proposed and examined. The FDM design is identified as the best, outperforming the BST and DG design by 1.93% and 5.13% for the transition delay.

With the continuous downscaling of transistors, stacked transistors are considered as the most important candidate for next-generation technology due to their area-efficient nature of 3-D stacking of n/p field effect transistor (FET) at the same footprint. Previously, we reported the Flip FET (FFET) as a new approach on stacking, with unique back-to-back stacking and much more manufacturing-friendly processes compared to the monolithic complementary field effect transistor (CFET) (Mono. CFET). In this work, we further explore the potentials and challenges of the FFET in the aspects of process developments, such as fin etch, wafer bonding and flipping, substrate thinning, active fin profile optimization, thermal budgets, and metal contaminations. The FFET architecture was further extended to nanosheets. Moreover, for the thermal budget and contamination concerns, novel Multi-flipping processes (Double Flips and Triple Flips) were proposed and investigated. By carefully choosing metals/dielectrics options, the Double Flips processes show the best balancing among processes complexity, cost, and power performance (PP). Moreover, detailed comparisons on high aspect ratio (HAR) processes and PP between the FFET and the Mono. complementary field effect transistor (CFET) were conducted, proving greatly relaxed process complexity and electrical advantage in the FFET.

In this work, a thorough design technology co-optimization (DTCO) study was conducted on stacked transistors for A10 and A7 nodes, focusing on their unique design challenges from dual-sided power rails (PRs) and high-aspect-ratio interlayer vias (super vias). The overlapped PR configuration is more applicable to the stacked transistor layout design than the staggered PR one with at least 3.41% higher frequency at iso-leakage,thanks to its relaxed limits on nanosheet (NS) width (W ${}_{\text {NS}}\text {)}$ . Simultaneously, the placement of super vias including drain merge (DM) and gate merge (GM) was carefully studied for its impact on the parasitic RC and design space of W_NS, thereby affecting the circuit-level performance. For A10 node with the 3.5T cell design, optimal performance can be realized when the DM and GM are placed on opposite sides of the active region for less overlap capacitance, offering a further 9.0% frequency gain through fine tuning the DM width (W ${}_{\text {DM}}\text {)}$ , GM width (W ${}_{\text {GM}}\text {)}$ , W_NS, and NS number (N ${}_{\text {NS}}\text {)}$ . However, for 2.5T design, it performs the best when the DM and GM are placed on the same side for the lager W_NS in this configuration. Similarly, at A7 node with even more constrained W_NS, same-sided DM and GM placement performs the best for both 3.5T and 2.5T cells. Finally, the novel stepped-channel structure was introduced, with the conflict between W_NS and GM process solved and bringing 1.2% frequency benefit.