Due to severer transistor aging at nanoscale, circuit design margin becomes extremely tight for advanced technology nodes. Thus, reliability-aware circuit design is urgently needed. In this article, a new framework to perform aging-aware static timing analysis (STA) is presented for reliability analysis. The key parts of aging-aware STA flows are workload analysis and aged delay/transition calculation. For the workload analysis, a new analytical stress probability (SP) calculation model is proposed, which considers the floating effect and signal correlations. For aged delay/transition calculation, a new aging-aware model is developed, which is accessible to large industrial libraries. The results show that the proposed model achieves high accuracy in the degradation estimation and aged-path-delay calculation. Due to its high accuracy and scalability, the proposed framework is a promising solution that is compatible with commercial Electronic Design Automation (EDA) tools.

Previous works on transistor reliability are mostly devoted to ON-state degradations, such as bias temperature instability and hot carrier degradation, for which physical models have been developed to describe corresponding mechanisms. However, very limited data on OFF-state degradation is available, especially in FinFET technology. In the first part of this article, OFF-sate degradations of 7-nm FinFET technology are reported for the first time. The physics mechanisms in OFF-state degradation are proposed by combining TCAD simulations and comprehensive experimental characterizations. It is found that an enhanced secondary carriers effect is responsible for the OFF-state degradation with contributions from both trapped electrons and holes. Furthermore, typical locations of electron traps and hole traps under the OFF-state degradation are identified. The abnormal leakage degradation is explained in a consistent manner. The analysis here leads to a compact reliability model reported in part II.

The self-heating effect (SHE) is a critical issue in nanoscale fin field effect transistors (FinFETs) that has emerged as an essential concern for device reliability. In physical circuit operations, devices generally suffer from mixed-mode hot carrier degradation (HCD) and bias temperature instability (BTI) stress conditions. The transient SHE at the HCD stage affects the BTI, resulting in an inadequacy of existing aging models. In this article, we develop an accurate transient self-heating model and incorporate it into a mixed-mode HCD-BTI reliability aging prediction framework. The transient SHE on the reliability of nanoscale p-type FinFETs are revealed thoroughly with experimental characterizations and accurate modeling. Circuit aging simulations with the developed transient SHE-aware aging prediction framework are presented. These results enable a more accurate reliability evaluation in state-of-the-art circuit designs.

With transistor scaling to nanometer region, aging effects become a non-neglectable issue in circuit design. Agingaware standard cell library is necessary for robust circuit design. To consider aging effects in standard cell libraries, existing methods mostly require simulating all combinations of aging variables and timing arcs, which are unscalable to large cells. In this paper, we propose an efficient aging-aware standard cell library characterization framework based on sensitivity analysis. We introduce the concept of critical transistors, which can be extracted by sensitivity analysis. By specifying these critical transistors, the number of SPICE simulations can be significantly reduced during the characterization of the aging-aware library. Experimental results on characterizing the standard cells in 16/14nm technology node demonstrate that the proposed method can achieve 1% average relative error and 1.48% maximum relative error with 4.9× to 305× speedup, compared with the state-of-the-art work. The method is very flexible and can be deployed into commercial electronic design automation (EDA) tools and libraries.

Reliability-enhanced circuit design is increasingly demanded due to severer transistor aging and variations at nanoscale. In this brief, new insights of inherently enhancing reliability are presented, based on the emerging computing paradigm of stochastic computing (SC). A new cross-layer reliability simulation flow supporting statistical static timing analysis (SSTA) is proposed, with a new long-term compact transistor aging model validated by 16/14nm FinFET experimental data. Then, the reliability of SC circuits in practical applications is investigated and compared with that of conventional binary circuits, for the first time. The results indicate that, the performance of SC circuits is intrinsically resistant to aging and variations ascribed to the circuit topology and the probability encoding. It suggests that, SC can provide more relaxed circuit design margins, offering promises to the application of emerging nanodevices in the future.

Part I of this article revealed that the OFF-state degradation consists of both bias temperature instability (BTI) and hot carrier degradation (HCD) traps in different channel regions. In part II of this article, a compact aging model of OFF-state degradation in advanced FinFETs is developed and validated by silicon data of 7-nm node, including the degradation and recovery phases. The model is capable to cover various types of devices, such as n/p types, core/IO devices, with short/long-channels. Meanwhile, trap contributions over time in different types of FinFETs are discussed based on the model component analysis. The model is implemented into circuit simulators and used to predict circuit aging with OFF-state degradation, for example, a ring oscillator (RO) circuit. The extrapolation result shows that up to 25% degradation is underestimated if the OFF-state reliability is not considered. This work provides a solution for more accurate reliability evaluation of nanoscale circuit design.