Dr. Chaitanya Mahajan is a materials scientist and process engineer specializing in electrochemistry, corrosion science, advanced alloys, and electrodeposition. He earned his Ph.D. in Materials Science and Engineering from the University of North Texas, Denton, TX, where his doctoral research focused on corrosion mechanisms in metallic glass coatings, high-entropy alloys (HEAs), and electrocatalytic performance of amorphous metallic systems. His academic work spans corrosion behavior in molten salt environments relevant to concentrating solar power systems, biocompatible metallic glass coatings for physiological applications, and the electrocatalytic properties of model metallic glasses for hydrogen oxidation reactions. Currently, Dr. Mahajan applies his expertise in advanced semiconductor manufacturing at Lam Research, where he develops and optimizes electroplating processes for advanced packaging platforms including Through-Silicon Via (TSV), Wafer-Level Packaging (WLP), and Panel-Level Packaging (PLP), leveraging computational tools such as COMSOL for hardware-process co-optimization.
Dr. Chaitanya Mahajan is a materials scientist and process engineer specializing in electrochemistry, corrosion science, advanced alloys, and electrodeposition. He earned his Ph.D. in Materials Science and Engineering from the University of North Texas, Denton, TX, where his doctoral research focused on corrosion mechanisms in metallic glass coatings, high-entropy alloys (HEAs), and electrocatalytic performance of amorphous metallic systems. His academic work spans corrosion behavior in molten salt environments relevant to concentrating solar power systems, biocompatible metallic glass coatings for physiological applications, and the electrocatalytic properties of model metallic glasses for hydrogen oxidation reactions. Currently, Dr. Mahajan applies his expertise in advanced semiconductor manufacturing at Lam Research, where he develops and optimizes electroplating processes for advanced packaging platforms including Through-Silicon Via (TSV), Wafer-Level Packaging (WLP), and Panel-Level Packaging (PLP), leveraging computational tools such as COMSOL for hardware-process co-optimization.