Ternary content-addressable memory (TCAM) is critical for applications requiring high-speed data retrieval and pattern matching, such as networking, cybersecurity, artificial intelligence, and real-time data analytics. While recent advancements in TCAM architectures have addressed challenges related to power consumption and scalability, significant potential for further optimization remains, particularly in enhancing energy efficiency and cell density. In this paper, we introduce TRIO-TCAM, a novel area- and energy-efficient TCAM architecture that utilizes a 10-transistor SRAM cell. Building on and surpassing the performance of state-of-the-art (SOTA) designs, TRIO-TCAM, designed using 28nm FD-SOI technology, achieves a 7.6% reduction in cell area. Moreover, it reduces searching delay by up to 37.4%, searching energy per bit by as much as 67.6%, and cell leakage by more than 41.7% compared to SOTA designs. These advancements position TRIO-TCAM as a promising solution for high-density, low-power TCAM applications in future high-performance systems.

Binary neural networks (BNNs) that use 1-bit weights and activations have garnered interest as extreme quantization provides low power dissipation. By implementing BNNs as computation-in-memory (CIM), which computes multiplication and accumulations on memory arrays in an analog fashion, namely, analog CIM, we can further improve the energy efficiency to process neural networks. However, analog CIMs are susceptible to process variation, which refers to the variability in manufacturing that causes fluctuations in the electrical properties of transistors, resulting in significant degradation in BNN accuracy. Our Monte Carlo simulations demonstrate that in an SRAM-based analog CIM implementing the VGG-9 BNN model, the classification accuracy on the CIFAR-10 image dataset is degraded to below 50% under process variations in a 28 nm FD-SOI technology. To overcome this problem, we present a variation-aware BNN framework. The proposed framework is developed for SRAM-based BNN CIMs since SRAM is most widely used as on-chip memory; however, it is easily extensible to BNN CIMs based on other memories. Our extensive experimental results demonstrate that under process variation of 28 nm FD-SOI, with an SRAM array size of $128\times 128$, our framework significantly enhances classification accuracies on both the MNIST hand-written digit dataset and the CIFAR-10 image dataset. Specifically, for the CONVNET BNN model on MNIST, accuracy improves from 60.24% to 92.33%, while for the VGG-9 BNN model on CIFAR-10, accuracy increases from 45.23% to 78.22%.

Some applications, such as satellites, require ultralow power and high-radiation resilience. We developed a12Tsoft error-resilient SRAM cell, TA-Quatro, to deliver in-memory computing (IMC) for those applications. Based on our TA-Quatro cell, we implemented an IMC circuit to support binary weights and ternary activations in a single SRAM cell. Our simulation under 28 nm FD-SOI technology demonstrates that the TA-Quatro IMC circuit maintains good IMC stability at a scaled supply of 0.7Vand achieves ternary activation without needing analog-to-digital converters. These advancements significantly enhance the power efficiency of the proposed IMC circuit compared to state-of-the-art works.

The significant data movement between processing units and DRAM adversely affects the performance and energy efficiency of the systems to process bulk bitwise logical operations (BLOs). Researchers have addressed the problem by employing processing-in-memory (PIM) techniques, where bulk bitwise operations are processed in DRAM. Among existing techniques, semi-digital PIMs, which support bulk BLOs by utilizing DRAM core circuits, are one of the most viable designs due to their moderate area penalties. However, our study reveals that state-of-the-art (SOTA) semi-digital PIMs suffer from considerable computation errors caused by process variations. This paper presents PABLO, a novel PIM architecture based on DRAM, to address the challenge. The essential contribution is to develop a generic bitwise unit integrated with the conventional local sense amplifier, enabling bulk BLOs with minimal overhead and modifications of commodity DRAM. As a result, the proposed design allows for simplified bitwise operations while hardly affecting conventional DRAM core operations. We comprehensively demonstrate the enhanced variation tolerance of PABLO compared to SOTA semi-digital PIMs through Monte Carlo simulations. Furthermore, our evaluation results indicate that PABLO achieves a speedup of up to ∼3.97× and energy savings of up to ∼3.87× compared to existing solutions

This paper presents an efficient in-memory hyperdimensional computing (HDC) design based on spin transfer-torque magnetoresistive RAM (STT-MRAM), named STT-HDC. A novel time-domain sense amplifier circuit is proposed that significantly simplifies Hamming distance computation of HDC models while dramatically improving energy efficiency. Our design is evaluated using HSPICE simulation under the 28nm FD-SOI technology PDK (Process Design Kit). Simulation results indicate that our approach delivers an energy efficiency of 3.12(fJ) per bit, achieving highly reduction in energy consumption relative to previous implementations. This substantial enhancement in energy performance, coupled with the simplified computation model, paves the way for more practical and scalable HDC systems in resource-constrained environments. The influence of variations in different process corners, and temperature impacts are also thoroughly covered in the analysis.