The significant data movement between processing units and DRAM adversely affects the performance and energy efficiency of the systems to process bulk bitwise logical operations (BLOs). Researchers have addressed the problem by employing processing-in-memory (PIM) techniques, where bulk bitwise operations are processed in DRAM. Among existing techniques, semi-digital PIMs, which support bulk BLOs by utilizing DRAM core circuits, are one of the most viable designs due to their moderate area penalties. However, our study reveals that state-of-the-art (SOTA) semi-digital PIMs suffer from considerable computation errors caused by process variations. This paper presents PABLO, a novel PIM architecture based on DRAM, to address the challenge. The essential contribution is to develop a generic bitwise unit integrated with the conventional local sense amplifier, enabling bulk BLOs with minimal overhead and modifications of commodity DRAM. As a result, the proposed design allows for simplified bitwise operations while hardly affecting conventional DRAM core operations. We comprehensively demonstrate the enhanced variation tolerance of PABLO compared to SOTA semi-digital PIMs through Monte Carlo simulations. Furthermore, our evaluation results indicate that PABLO achieves a speedup of up to ∼3.97× and energy savings of up to ∼3.87× compared to existing solutions

Peripheral nerve electrical stimulation is widely used for the treatment of neuropathic pain and neural regeneration. However, it often induces adverse biological reactions and unintended activation of surrounding neural tissues. As an alternative, peripheral nerve magnetic stimulation offers a promising, less invasive approach that enables targeted nerve stimulation without direct tissue contact. Despite its potential, it is constrained by the bulkiness of coils and excessive heat generation due to the high currents required. To address these limitations, we conducted a study on coil design optimized for peripheral nerve modulation. Our approach, supported by simulations and animal experiments, focused on optimizing coil geometry to maximize the induced electric field gradient. Among various designs, a four-leaf rhombus-shaped coil demonstrated the highest gradient at the center of the interface. In rat sciatic nerve experiments, this coil, driven by a rectangular pulse with a 200 μs rise time and 25 V amplitude, successfully elicited compound muscle action potentials in both the tibial anterior and gastrocnemius muscles. This study presents design guidelines for peripheral nerve stimulation (PNS) coils based on magnetic stimulation as an alternative to conventional electrical stimulation. The proposed approach may serve as a foundation for the development of advanced, miniaturized, and energy-efficient neural stimulation coils.

This article presents an energy-autonomous, self-resetting, multi-node temperature sensor powered by hybrid energy harvesting. The ultra-low leakage Self-Adaptive Full Bridge Rectifier (SA-FBR) accepts any hybrid energy harvesting source at both sparse and abundant inputs and suppresses the leakage by 1000×. The Dynamic Power Management Unit (D-PMU) enables event-driven wake-up capability that allows for 97.3% power saving during standby mode. The 0.5 nJ/conversion temperature sensor in 0.18 μm CMOS uses active self-resetting, spike-based coding to achieve the widest measurement range of -10∘C to 110∘C to date.

This paper introduces a fully integrated gate-pole-dominant low-dropout regulator (LDO) that eliminates the need for external capacitors while sustaining high power-supply rejection (PSR) over a broad load current range. A loop-gain booster (LGB) is proposed to maintain the DC operating point of the error amplifier output at its optimal value, thereby preserving a high unity-gain frequency (UGF) even as the load current varies from zero to 200 mA. The parallel signal paths within the LGB inherently produce a left-half-plane (LHP) zero, which cancels one of the poles within the UGF of the feedback loop and guarantees robust stability under diverse operating conditions. Fabricated in a 40 nm CMOS technology, the prototype occupies only 0.008 mm² with a 4 pF on-chip compensation capacitor. The proposed LDO achieves a PSR of −72 dB at 1 MHz and −40 dB at 10 MHz when I_L = 200 mA and V_DO = 0.1 V, and maintains a PSR better than −78 dB at 1 MHz and −42 dB at 10 MHz when I_L = 1 mA and V_DO = 0.1 V. The LGB-enhanced regulator achieves excellent load and line regulation figures of 29 μV/mA and 0.75 mV/V, while the LGB itself consumes merely 7 μA out of a total quiescent current of 108 μA.

Microscopic magnetic stimulation (MSTI) induces electric fields without direct charge injection and can shape localized field gradients with asymmetric micro-coils. Most demonstrations still rely on external drivers, off-chip hardware, or separated coil validation, so the CMOS integration boundary remains poorly characterized. This work presents a fabricated $2\times 1 {\mathrm{mm}}^2$ $0.18 \mathsf{\mu }\mathrm{m}$ CMOS magnetic-stimulation SoC that co-integrates ASK-compatible command decoding, FSM and register-based parameter control, a programmable current–voltage–current triangular driver, and a bent top-metal micro-coil, and it characterizes the on-chip driver-to-coil path together with a substrate-aware field model. Sensing-load reconstruction confirms command-to-waveform programmability, including duration-window decoding, burst-count control, and polarity reversal, with measured slew targets that give a peak current of $I_{\mathrm{pk}}=3.72$–$21.6 \mathrm{mA}$. A quantitative comparison contrasts the current-mode triangular driver with conventional electrode stimulators, a coil-impedance measurement shows the coil stays resistive across 1 to 10 MHz, and the measured total SoC power is about 41 mW. Substrate-aware simulation at a $15 \mathsf{\mu }\mathrm{m}$ target plane shows that the grounded p-substrate retains $35.1$–$40.5\%$ of the no-substrate peak x-directed field-gradient metric. The prototype establishes this electrical programmability and the substrate-aware gradient-transfer loss as a compact design-margin metric for CMOS-integrated magnetic stimulation. Direct biological activation is not claimed and is left to future in vitro validation.