Dr. Purushothaman Srinivasan
Global Reliability, GlobalFoundries (United States), Santa Clara, California, USA
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Academic Career Length
23Years (2004-Present)
(Calculated once Scilit publication data is synced: current year − year of first publication + 1)
Representative Publications
View All Publications7 April 2009 in IEEE Transactions on Device and Materials Reliability
Journal Article
PMP. Magnone
P. MagnoneFCF. Crupi
F. Crupi
GGG. Giusi
G. Giusi
CPC. Pace
C. PaceESE. Simoen
E. Simoen
Purushothaman Srinivasan +4
In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implemented as gate dielectrics. We evaluate both drain- and gate-current noises in order to obtain information about the defect content of the gate stack. We analyze how the overall quality of the gate stack depends on the kind of high-k material, on the interfacial layer thickness, on the kind of gate electrode material, on the strain engineering, and on the substrate type. This comprehensive study allows us to understand which issues need to be addressed in order to achieve improved quality of the gate stack from a 1/f noise point of view.
24 July 2006 in IEEE Electron Device Letters
Journal Article
FCFelice Crupi
Felice CrupiPurushothaman SrinivasanPMP. Magnone
P. MagnoneESE. Simoen
E. Simoen
CPC. Pace
C. PaceCCC. Claeys
C. Claeys +1
The impact of the interfacial layer thickness on the low-frequency (LF) noise (1/f noise) behavior of n- and p-channel MOSFETs with high-kappa gate dielectrics and metal gates is investigated. Decreasing the interfacial layer thickness from 0.8 to 0.4 nm affects the 1/f noise in two ways. 1) The mobility fluctuations mechanism becomes the main source of 1/f noise not only on pMOS devices, as usually observed, but also on nMOS devices. 2) A significant increase of the Hooge's parameter is observed for both types of MOSFETs. These experimental findings indicate that bringing the high-kappa layer closer to the Si-SiO2 interface enhances the 1/f noise mainly due to mobility fluctuations
1 December 2017
Conference Paper
SNS. Narasimha
S. Narasimha
BJB. Jagannathan
B. Jagannathan
AOA. Ogino
A. Ogino
DJD. Jaeger
D. Jaeger
BGB. Greene
B. Greene
DSD. K. Sohn
D. K. Sohn
+148
We present a fully integrated 7nm CMOS platform featuring a 3rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization. This technology reflects an improvement of 2.8X routed logic density and >40% performance over the 14nm reference technology described in [1-3]. A full range of Vts is enabled on-chip through a unique multi-workfunction process. This enables both excellent low voltage SRAM response and highly scaled memory area simultaneously. The HD 6-T bitcell size is 0.0269um2. This 7nm technology is fully enabled by immersion lithography and advanced optical patterning techniques (like SAQP and SADP). However, the technology platform is also designed to leverage EUV insertion for specific multi-patterned (MP) levels for cycle time benefit and manufacturing efficiency. A complete set of foundation and complex IP is available in this advanced CMOS platform to enable both High Performance Compute (HPC) and mobile applications.
21 August 2006 in IEEE Transactions on Electron Devices
Journal Article
FCF. Crupi
F. Crupi
BKB. Kaczer
B. Kaczer
RDR. Degraeve
R. Degraeve
VSV. Subramanian
V. Subramanian
Purushothaman SrinivasanGGG. Groeseneken
G. Groeseneken +3
A comparative study of the reliability issues of triple-gate and planar FETs processed on the same silicon-on-insulator wafer is presented. It is shown that the triple-gate architecture does not alter the behavior of the time-dependent dielectric breakdown (BD) for different gate voltages and temperatures. The apparent higher Weibull slope observed in planar devices with respect to the triple-gate devices is ascribed to the area dependence of the time-to-BD detection. In spite of the different surface orientations, low-frequency noise measurements indicate similar values of the interface trap density for triple-gate and planar FETs
1 January 2011 in The Electrochemical Society Interface
Journal Article
YOYaw Obeng
Yaw Obeng
Purushothaman SrinivasanA summary of the graphene component of the ECS symposia series on “Graphene, Ge/III-V, Nanowires, and Emerging Materials for Post-CMOS Applications” is provided. While not exhaustive and complete, a review of the papers presented at these symposia provides a brief glimpse of the state of graphene research over the last few years.
1 June 2005 in Microelectronic Engineering
Journal Article
Purushothaman SrinivasanESE. Simoen
E. Simoen
LPL. Pantisano
L. Pantisano
CCC. Claeys
C. Claeys
DMD. Misra
D. Misra
About Me
Purushothaman Srinivasan (SP) is currently a Senior Member of Technical Staff (SMTS) working as a RF reliability team leader for CMOS Si technologies, at GLOBALFOUNDRIES, Malta, NY. He is currently focused on RF reliability in advanced CMOS nodes (45, 22, 14/12nm nodes). He was also a GLOBALFOUNDRIES assignee member at IBM, Albany until 2015. His research areas include high-k metal gate, SiGe-based transistors, Negative Bias Temperature Instability, low frequency (1/f) noise and Random Telegraph Signals (RTS). From 2007-2012, he was a Research Staff Member at Texas Instruments, Dallas and was an adjunct professor in the MSE department at University of Texas, Dallas from 2010-2012. Since 2008, he has been an Executive Committee member of Dielectric Science and Technology Division at Electrochemical Society. He has been serving the IRPS transistor sub-committee
since 2017 and served the Process Integration sub-committee in 2019. Prior to joining TI, he obtained his PhD degree from IMEC, Leuven, Belgium and New Jersey Institute of Technology, Newark, NJ. He is also a senior member of IEEE, holds IEEE membership for 15 years, has edited five books, holds 5 patents, >25 invited talks authored and co-authored more than 150 international publications with over 1000 citations. His conference publications include top tier
conferences at IEDM and VLSI. He currently as a reviewer for at least six journals, including the Journal of The Electrochemical Society and IEEE TED, EDL, JEDS.
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