In this article, FinFET, vertically stacked gate-all-around (GAA) nanowire (NW), and nanosheet (NS) FETs performance are estimated with equal effective channel widths ( $\textit{W}_{\text{eff}}\text{)}$ at the 5-nm technology node (N5). The comparison reveals that NS FET exhibits the highest ON current ( $\textit{I}_{\biosc{on}}\text{)}$ , the lowest OFF current ( $\textit{I}_{\biosc{off}}\text{)}$ , and the largest $\textit{I}_{\biosc{on}}$ / $\textit{I}_{\biosc{off}}$ ratio with better subthreshold performance. We also explore the geometrical variation of the NS FET toward better dc and analog/RF applications and outlined the necessary design guidelines. Moreover, the robustness of NS FET for temperature variations is also performed and analyzed. Finally, the effect of NS width (NS $_{\textit{W}}\text{)}$ on common source (CS) amplifier, CMOS inverter, and ring oscillator circuits is performed by the Verilog-A model in the CADENCE simulator. An increment of 45.11% in oscillation frequency ( $f_{\text{osc}}\text{)}$ , 155.5% rise in CS amplifier gain, 2.5 $\times$ increment in energy-delay product (EDP), and marginal reduction in inverter noise margin (NM) is noticed with larger NS $_{\textit{W}}$ . From the result analysis, it is noticed that for sub-5-nm technological nodes, NS FETs exhibit superior performance and ensure fundamental scaling.

In this study, for the very first time developing of n- and p-type 3-D single-channel (SC) FinFET and gate-all-around (GAA) Multi-Bridge-Channel FETs (MBCFET) like nanowire FET (NWFET) and nanosheet FET (NSFET) are benchmarked towards device and circuit levels which are emulated with International Road map for Devices and Systems (IRDS) for sub-5-nm technology nodes. Compared to the FinFET, the MBCFETs exhibits higher ON-current ( $I_{\mathrm {ON}})$ , switching ratio ( $I_{\mathrm {ON}}/I_{\mathrm {OFF}})$ , lower subthreshold-swing (SS) and drain-induced barrier lowering (DIBL). Except for extended parasitic capacitances ( $C_{\mathrm {para}})$ , our benchmarking results show that the NWFET and NSFET achieve the high-performance (HP) and low-power (LP) goals of IRDS. Furthermore, the NSFET delivers superior performance towards DC and analog/RF metrics. The cut-off frequency ( $f_{\mathrm {T}})$ and gain bandwidth product (GBW) are higher (because of high $I_{\mathrm {ON}})$ in the case of NSFET, even though the capacitive effect is significant. Further, the logic circuit applications like CMOS inverter and ring oscillator (RO) circuits are analyzed and compared in detail. The CMOS inverters propagation delays ( $\tau _{\mathrm {p}})$ is reduced to 31% from FinFET to NWFET and 12% from NWFET to NSFETs is noticed. Also, the NWFET and NSFET based ROs offer 39% and 56% high oscillation frequency ( $f_{\mathrm {osc}})$ compared to that of FinFET counterpart. Finally, the single stage current mirror performance and operational transconductance amplifiers (OTA) gain and common mode rejection ratio (CMRR) are carried out towards analog and mixed-mode circuit applications.

This work investigates the effect of single and dual- k spacer materials consisting of different dielectric constants ( k ) in optimized nano-channel gate-stack nanosheet (NS-FET) employing hafnium oxide and silicon dioxide as gate insulator to improve its sub-threshold performance. The effect of the external low-k spacer modification in the dual-k spacer has been shown by adjusting the inner high-k spacer. The drain-induced barrier lowering (DIBL) in this modification with dual-k spacer is 14 mV/V, which is a significant improvement above single spacer NS-FET. The Visual TCAD 3D Cogenda tool is used to examine the performance of the developed NS-FET with air, single, dual-k, and hybrid spacers. The CADENCE platform is used to perform circuit aspects. Additionally, a comparison of the device architecture’s performance study with respect to DC characteristics is made. DC parameters of the proposed device are established: I_ON to I_OFF ratio of approximately 10 ⁵ , DIBL of approximately 14 mV/V, sub-threshold swing (SS) of approximately 62 mV/dec, and low threshold voltage (Vth) of 0.38 V. The analysis on power consumption for advanced NS-FET is also analyzed with single- k and dual- k spacers. The performance of single- k and dual- k spacer dielectric variation for CMOS inverter is also shown. Furthermore, low power consumption by this NS-FET ensures improved device performance suitable for nanoscale semiconductor industries.