Arguably, the integrated circuit (IC) industry has received robust scientific and technological attention due to the ultra-small and extremely fast transistors since past four decades that consents to Moore's law. The introduction of new interconnect materials as well as innovative architectures has aided for large-scale miniaturization of devices, but their contributions were limited. Thus, the focus has shifted toward the development of new integration approaches that reduce the interconnect delays which has been achieved successfully by three-dimensional integrated circuit (3D IC). At this juncture, semiconductor industries utilize Cu–Cu bonding as a key technique for 3D IC integration. This review paper focuses on the key role of low temperature Cu–Cu bonding, renaissance of the low temperature bonding, and current research trends to achieve low temperature Cu–Cu bonding for 3D IC and heterogeneous integration applications.

Optimally engineered ultra-thin gold (Au) layer as an effective surface passivation for low temperature, low pressure fine pitch Cu-Cu bonding is demonstrated in this work. The Au passivation layer not only performs the role of protecting the underlying Cu surface from unwanted oxidation but it also helps in reducing the effective surface roughness, which are two major requirements for thermocompression bonding. Additionally, Au, being a noble metal, ensures efficient surface passivation of Cu even at elevated temperatures. Furthermore, Au passivated Cu surfaces show significantly high 111 oriented surface planes with random grain structures at the bonding interface, which account for enhanced diffusion ability. Herein, an optimized Au passivation layer of 3 nm has resulted in high quality fine pitch Cu-Cu thermocompression bonding at 140 °C and 0.3MPa pressure. The bonded samples have further been subjected to various reliability studies in order to confirm the efficacy of the proposed bonding scheme, along with mathematical modeling to cross check using Fick’s second law of approximation. The bonded samples have attributed to a high bond strength (>200MPa) and a very low and stable specific contact resistance (~1.43 × 10-8 Ω-cm2) at robust conditions, which is significantly better than the values previously reported in literature.

In this study, for the very first time developing of n- and p-type 3-D single-channel (SC) FinFET and gate-all-around (GAA) Multi-Bridge-Channel FETs (MBCFET) like nanowire FET (NWFET) and nanosheet FET (NSFET) are benchmarked towards device and circuit levels which are emulated with International Road map for Devices and Systems (IRDS) for sub-5-nm technology nodes. Compared to the FinFET, the MBCFETs exhibits higher ON-current ( $I_{\mathrm {ON}})$ , switching ratio ( $I_{\mathrm {ON}}/I_{\mathrm {OFF}})$ , lower subthreshold-swing (SS) and drain-induced barrier lowering (DIBL). Except for extended parasitic capacitances ( $C_{\mathrm {para}})$ , our benchmarking results show that the NWFET and NSFET achieve the high-performance (HP) and low-power (LP) goals of IRDS. Furthermore, the NSFET delivers superior performance towards DC and analog/RF metrics. The cut-off frequency ( $f_{\mathrm {T}})$ and gain bandwidth product (GBW) are higher (because of high $I_{\mathrm {ON}})$ in the case of NSFET, even though the capacitive effect is significant. Further, the logic circuit applications like CMOS inverter and ring oscillator (RO) circuits are analyzed and compared in detail. The CMOS inverters propagation delays ( $\tau _{\mathrm {p}})$ is reduced to 31% from FinFET to NWFET and 12% from NWFET to NSFETs is noticed. Also, the NWFET and NSFET based ROs offer 39% and 56% high oscillation frequency ( $f_{\mathrm {osc}})$ compared to that of FinFET counterpart. Finally, the single stage current mirror performance and operational transconductance amplifiers (OTA) gain and common mode rejection ratio (CMRR) are carried out towards analog and mixed-mode circuit applications.

We report the fabrication of a flexible, lightweight and disposable multi walled carbon nanotube (MWCNT)–zinc oxide (ZnO) nanofiber based chemiresistive biosensor for label free detection of the malaria biomarker, histidine rich protein II (HRP2). The sensing platform is formed by depositing nanofibers in between the source and drain electrodes patterned on a thin, flexible polyethylene terephthalate (PET) substrate. MWCNT–ZnO nanofibers are synthesized via the electrospinning technique followed by a calcination process. This approach creates functional groups on the nanofiber surface that are used for the one step immobilization of HRP2 antibodies without further surface modification. The device exhibits a good sensitivity of 8.29 kΩ g⁻¹ mL and a wide detection range of 10 fg mL⁻¹–10 ng mL⁻¹, and it is specific towards the targeted HRP2 biomarker. To the best of our knowledge, this is the first report on a flexible chemiresistive biosensor explored for the detection of the malaria biomarker and can be extended in the future to several other biomarker detection systems towards smart point-of-care (POC) diagnostics.

This work investigates the effect of single and dual- k spacer materials consisting of different dielectric constants ( k ) in optimized nano-channel gate-stack nanosheet (NS-FET) employing hafnium oxide and silicon dioxide as gate insulator to improve its sub-threshold performance. The effect of the external low-k spacer modification in the dual-k spacer has been shown by adjusting the inner high-k spacer. The drain-induced barrier lowering (DIBL) in this modification with dual-k spacer is 14 mV/V, which is a significant improvement above single spacer NS-FET. The Visual TCAD 3D Cogenda tool is used to examine the performance of the developed NS-FET with air, single, dual-k, and hybrid spacers. The CADENCE platform is used to perform circuit aspects. Additionally, a comparison of the device architecture’s performance study with respect to DC characteristics is made. DC parameters of the proposed device are established: I_ON to I_OFF ratio of approximately 10 ⁵ , DIBL of approximately 14 mV/V, sub-threshold swing (SS) of approximately 62 mV/dec, and low threshold voltage (Vth) of 0.38 V. The analysis on power consumption for advanced NS-FET is also analyzed with single- k and dual- k spacers. The performance of single- k and dual- k spacer dielectric variation for CMOS inverter is also shown. Furthermore, low power consumption by this NS-FET ensures improved device performance suitable for nanoscale semiconductor industries.