Future hyper-connected devices must support several communication standards, across various frequency bands, with a low-area, single-chip, radio frequency frontend. In this paper, we present a reconfigurable, inductorless, wide-band, low-noise amplifier (LNA) for multistandard applications. This LNA is based on a complementary current-reuse common source amplifier, combined with a low-current active feedback. A gyrator-C effect is used to achieve wideband input matching. High linearity is obtained through complementary derivative superposition and active shunt feedback. Implemented in 130-nm CMOS technology, the prototype exhibits a -3 dB bandwidth of 2.2 GHz. In high linearity mode, the LNA achieves a minimum NF of 2 dB, a voltage gain of 21.1 dB and an I I P ₃ of +14.3 dBm, with 7 mW of power consumption. In low-power mode, it draws 1.5 mW, while providing a NF of 2.6 dB, a gain of 21 dB, and an I I P ₃ of 4.7 dBm. The active die area is 0.0072 mm ² .

Radiofrequency (RF) energy harvesting is a key technique that can be employed in systems for generating some amount of electrical power to drive circuits in wireless communicating devices or, even so, to power supply a full node in wireless sensor networks (WSNs). This paper presents the comparison between two different CMOS rectifier topologies operating in the 900 MHz and 2.4 GHz ISM bands to convert RF power into DC power, both implemented in a CMOS 130nm technology. The first one is a traditional voltage multiplier today commonly used for scavenging energy from RF sources and for RFID applications. The second one is a cross-coupled voltage multiplier, which achieves a significant improvement in power efficiency and low voltage-drop compared with the traditional circuit.

The Internet of Things (IoT) entails new challenges for the development of wireless transceivers. Radio-frequency building blocks require complex design flows in order to address very different sets of specifications. This paper presents a three-step design methodology dedicated to the synthesis of RF building blocks. Based on the inversion coefficient, the proposed design methodology allows the optimization of the circuit performance for any CMOS process and any application. It is illustrated through the implementation of inductorless low-noise amplifiers (LNA) in three different CMOS nodes: 28-nm fully-depleted silicon-on-insulator (FDSOI), and 65 and 130-nm Bulk. These LNAs are dedicated to two cases of IoT applications: multi-standard and ultra low power. The proposed circuits achieve the state-of-the-art performance for all nodes and applications. Furthermore, the methodology enables an insightful comparison of the capabilities of the different CMOS nodes in terms of power consumption, noise, and bandwidth.

The evolution of wireless communications technologies is fostering new Internet of Things (IoT) applications. However, sustainable IoT development requires new batteryless and eco-friendly device designs, contributing to cost reduction, lower maintenance, and less environmental damage compared to typical battery-powered IoT. Inspired by such goals, this paper presents a behavioral modeling of a radio frequency wireless power transfer (WPT) system for batteryless IoT applications. We consider a supercapacitor as the energy storage element and analytically describe its behavior during energy harvesting as well as during information transmission. To validate our proposed model, we compare it with measurement results from the literature, showing perfect agreement. Furthermore, we also compare the proposed model with the state-of-the-art, highlighting important differences when considering the effect of the elements preceding and succeeding the supercapacitor into the recharging time, which have critical implications in the design of charging and transmission cycles.

A millimeter-wave (mmW) chipset for 77-81 GHz automotive radar has been developed in 0.13μm SiGe HBT technology. This work presents the performances of an integrated Low Noise Amplifier (LNA), a Power Amplifier (PA), a down-converting Mixer, and also a Voltage Controlled Oscillator (VCO). For successful implementation of the circuit, considerations on the reliability of the design have been taken into account. Measurements on all circuits confirm the feasibility of mmW front-end using silicon based technologies for W-band application.

This paper discusses and compares the design of two high-efficiency 4-stage voltage-doubler UHF RFID rectifier operating at 915 MHz. The first rectifier uses conventional 180-nm CMOS transistors applying a technique of internal cancellation in order to compensate the high value of their threshold voltages (V _th ). The second proposed rectifier uses zero-V _th transistors, which are available in a 130 nm CMOS process, eliminating the need for compensation circuitry. The circuit implementing V _th compensation occupies a 0.025 mm ² area, achieving a -12 dBm input sensitivity and a 18% power conversion efficiency (PCE) when supplying a 1.2 V output voltage and a 10 μA load current. For the same load conditions, the circuit including zero-V _th transistors presents a reduced area occupation (0.013 mm ² ), while providing both improved sensitivity (-14.3 dBm) and a 33% PCE at this sensitivity.