The design of a Phase-Locked Loop (PLL) to generate the clock reference for the new Spacefibre standard is presented in this paper. Spacefibre has been recently released by the European Space Agency (ESA) and supports up to 6.25 Gbps for on-board satellite communications. Taking as a starting point a rad-hard 6.25 GHz Voltage Controlled Oscillator in 65 nm technology, this work presents the design of the key blocks for an integrated PLL: a Triple Modular Redundancy Phase/Frequency Detector, a Charge Pump, and a passive Loop Filter. The modeling activities carried out in an Advanced Design System have proven that the proposed PLL can be completely integrated on-chip, with a Loop Filter area consumption of only 6000 µm² (considering the 65 nm technology). The design of active circuits has been carried out at the transistor level in a Cadence Virtuoso environment, implementing both system and layout rad-hard techniques, and different solutions are discussed in this paper. As a result, a compact (0.09 mm²), low power (10.24 mW), dead zone free and rad-hard PLL is obtained with a Phase Noise below −80 dBc/Hz @ 1 MHz. A preliminary block view and floor plan of the test chip is also proposed.

The current trend of increasing the complexity of hardware accelerators to improve their functionality is highlighting the problem of sharing a high-frequency clock signal for all integrated modules. As the clock itself is becoming the main limitation to the performance of accelerators, in this manuscript, we present the design of an asymmetric Ring Oscillator-Voltage-Controlled Oscillator (RO-VCO) based on the Current Mode Logic architecture. The RO-VCO was designed on commercial-grade 65 nm CMOS technology, and it is capable of driving large capacitance loads, avoiding the need for additional buffers for clock-trees, reducing the silicon area and power consumption. The proposed RO-VCO is composed of three closed-loop differential and asymmetrical stages, and it is able to tune the working frequency in the range from 4.72 GHz to 6.12 GHz. The phase noise and a figure of merit of −103.2 dBc/Hz and −186 dBc/Hz were obtained at 1 MHz offset from the 5.5 GHz carrier. In this article, the analytical model, full custom schematic, and layout of the proposed RO-VCO are presented and discussed in detail together with the experimental electrical and thermal characterization of the fabricated device.

Among all the functions that electronics currently perform, clock synthesis has a backbone role. Charge pump phase-locked loops (CP-PLL) are widely used to accomplish clock synthesis thanks to their versatility. One of the most critical parts of CP-PLLs is the charge pump, which greatly influences the system’s performance. Even though several high-performance charge pumps have been proposed in the past, with the quick spread of electronics in all the engineering fields, the design of such electronic devices has encountered several additional challenges dictated by external environmental conditions. Examples of these engineering sectors are space, aerospace, industrial, and automotive applications, where the charge pump has to face high environmental temperatures and radiation effects. As a consequence, its design and experimental characterization have to be performed to ensure reliability when operating in harsh conditions. However, to the best of the authors’ knowledge, no works in the literature have ever presented a complete charge pump design and characterization in such harsh environments. Therefore, to fill this gap, this paper presents a charge pump for PLL applications specifically designed to reach operating temperatures up to 200 °C and total ionizing dose levels up to 100 Mrad. All design choices have been experimentally verified and are discussed throughout the paper in detail. With the proposed design, we obtained an output current variation of less than 8% at 200 °C and less than 2.5% at 100 Mrad. As opposed to the CPs that can be found in the literature, these results were measured on silicon. The performed measurements confirm that the current variation at 200 °C is better than that of the state-of-the-art CPs operating at lower temperatures, which, moreover, were only simulated.

Reliability is an important characteristic of electronic systems, and it could be undermined by several issues. Among these, wide temperature range represents a threat for the correct operation of electronic systems. Indeed, wide temperature ranges can be experienced in various fields, such as the oil and gas industry, the avionics and automotive fields, or space applications. In these cases, temperatures can reach maximum values up to 160 °C and minimum values down to -40 °C. Additionally, in these fields, the ever-improving sensors’ technology is pushing for increasingly higher data-rates to the control units. This implies the use of high-speed point-to-point connections, which usually exploit Phase-Locked Loops (PLL) to synchronize the communication. These PLLs should then be able to operate in harsh environments and in the GHz range. In this paper, we present the design and the experimental verification of a 6.25 GHz PLL for harsh-temperature conditions from -40 °C up to 160 °C prototyped in a standard 65 nm CMOS technology. We describe the transistor-level design, and we discuss the setups for all the performed measures. The proposed PLL shows a limited performance dependence on temperature variations, which can be compensated further thanks to a tunable bandwidth. Moreover, it achieves fast locking with low area, low power, and a Phase Noise below -98 dBc/Hz @ 1 MHz.

Links able to sustain high-speed data transfer while exposed to radiation phenomena are required by several applications, including aerospace and high-energy physics experiments. To satisfy this need, this paper outlines the design of a radiation-hard line driver for communication up to 10 Gb/s. The driver design is focused on the techniques adopted to increase its radiation hardness, namely the use of long-channel transistors, the avoidance of p-type MOSFETs and thick oxide devices. Circuital strategies to boost driver speed, such as inductive peaking, buffer chaining, and optimal layout placement and routing, are discussed and implemented to compensate for the downsides caused by adopted radiation-hard techniques. The driver, fabricated in 65 nm technology, has been experimentally tested demonstrating its ability to operate up to 10 Gb/s in a radiation-pervaded environment. In particular, after exposure to 1 Grad(SiO2) X-ray, the line driver exhibits an output signal amplitude reduction of 18.3% and a jitter increase of 5.53%. Performed temperature tests highlight that the line driver is capable to operate at 125 °C with 15.9% and 6.7% output signal swing reduction and jitter increase, respectively. The temperature tests also demonstrate the driver’s ability to work up to 160 °C with an output signal swing reduction below 25% and a jitter increase below 12%.

This paper compares two different architectures for implementing a sub-sampling phase-locked loop (SS-PLL). First, a time-domain model is used to analyze the noise contributions of the sampling mechanisms: voltage sampling (VS) and charge sampling (CS). Then, based on the obtained noise results, the performance of complete SS-PLL systems is evaluated using a phase-domain model. This approach applies to PLLs utilized as frequency synthesizers with large divide ratios (e.g., 64 to 512) as well as to SS-PLLs operating without a divider in their loop. Although the CS technique can theoretically enhance the Signal-to-Noise Ratio (SNR) by 3 dB compared to VS, the proposed phase-domain model highlights that, within typical power budgets ranging from 1 to 20 mW, a VS-PLL achieves a lower level of integrated jitter than a CS-PLL. This is due to the intrinsic noise of the charge sampling phase detector (CSPD) that, unlike in the VS-PLL, cannot be suppressed and therefore becomes the dominant in-band noise source.