In this paper, an ultra-wide output voltage reconfigurable LLC resonant DC-DC converter is presented for electric vehicle (EV) fast charging application. The proposed LLC topology design uses six operating modes for providing a wide output voltage from 100 V to 1100 V with a constant current (CC) output. The proposed circuit consists of a three-winding high-frequency transformer (HFT) connected with a MOSFET full bridge at the primary side and two voltage doubler diode rectifiers at the secondary side. Additionally, two MOSFETs and two diodes switch combinations at the output side reconfigure the two diode rectifiers outputs in three ways. Hence with full-bridge (FB) and half-bridge (HB) operations from the primary side, the proposed circuit provides a total of six-operating modes. The detailed step-by-step procedure is presented for designing a continuous output voltage range using six operating modes. The proposed converter has a low operation frequency range (OFR) and high magnetization to series resonating inductance ratio (MRR) of the LLC tank. The closed-loop operation of the converter is validated on PLECS for a 30 A CC output. The open-loop experimental results of a 700 W laboratory prototype are also presented to validate the six operating modes for ultra-wide output voltage gain.

This article proposes a novel nine-level multilevel inverter topology with an instantaneous voltage balancing scheme of stacked dc-link capacitors for an induction motor (IM) drive application. Three neutral points (NPs, terminal joints of four series-connected capacitors) across a single dc-link are balanced instantaneously (within a sampling interval) by ensuring zero current at the NPs. The proper selection of pole voltage from the redundancies provides zero current at any NP during the pulsewidth modulation operation under a steady-state and transient operation. A five-level stacked inverter and three cascaded hybrid-bridge (CHB) inverter cells are used in each phase. Along with the balancing of dc-link capacitors, CHB capacitors’ voltage balancing is also achieved using the pole voltage redundancies at all modulation indexes for all power factor and load. It is also possible to increase more number of levels using more low-voltage switches, and a generalized form of the topology is presented. The concept is validated using a laboratory-developed nine-level inverter with a three-phase IM load, operated under “V/f” control. The detailed experimental results for the steady and transient condition, simulation studies for switching loss, and harmonic content in the phase voltage are also presented.

In this article, a nine-level multilevel topology is proposed by stacking of low voltage basic inverter cells and then cascading with H-bridges. The dc-link is split into four equal halves by series-connected capacitors from a common dc-link. Three common coupling points (CCPs) are formed due to the stacking of four capacitors, which are connected across the dc-link. The CCP voltage balancing is ensured by drawing or injecting zero instantaneous currents from each of these points at any instant. A six-phase symmetrical IM is used to generate equal and opposite instantaneous phase currents by applying exactly equal and opposite phase voltages for two opposite phases from the six-phase inverter. Simultaneously, the capacitor voltage balancing of H-bridge inverter cells is also achieved by proper selection of redundancies from the available pole voltage redundancies. The concept is verified with a nine-level inverter laboratory prototype, which consists of a five-level stacked inverter, and followed by two low voltage cascaded H-bridge inverters in each phase. Detailed experimental results of steady-state and transient conditions are included to validate the proposed scheme.

This paper proposes a multilevel inverter topology with a single DC-link and series-connected capacitors as stacked voltage sources for multilevel voltage generation. The voltage deviation of a DC-link capacitor will occur whenever a phase terminal connects to the balanced neutral points (NPs: terminal joints of DC-link capacitors). On the contrary, if the voltage of a DC-link capacitor deviates from the nominal voltage, the same phase currents can be utilised to balance these neutral points. This new technique is being proposed for the first time in literature. Any voltage disturbance of the DC-link capacitors is balanced using the motor phase currents, irrespective of load power factor and modulation indices. For the balanced neutral points, whenever a phase connects to a neutral point, the other phase terminal tapping positions are varied on the DC-link to establish $i_{A}+i_{B}+i_{C}=0$ for that neutral point. The pole voltage level variation at motor phase terminals is undisturbed by adding extra cascaded H-bridges (CHBs) at each phase leg. The voltages of CHB capacitors are controlled conventionally by inverter pole voltage redundancies. The detailed experimental results for open-loop V/ f and closed-loop field-oriented control on an induction motor are presented using a nine-level laboratory prototype.

The voltage drift control of series-connected capacitors across a single DC-link is the major challenge for a multi neutral point clamped (NPC) converter. This drifting is caused due to uneven currents drawn from the neutral points during the PWM operation. This work presents the working principle of instantaneous voltage control of ‘ n ’ DC-link series-connected capacitors for an induction machine load. The mechanism of instantaneous voltage balancing is realised by ensuring zero instantaneous currents at each DC-link neutral point. To get zero instant currents at a DC-link NP branch, the phase terminals tapping on the DC-link are manipulated with the help of cascaded hybrid bridges (CHBs). Charge balancing of CHB capacitors is also taken care of by proper utilisation of pole voltage redundancies. The detailed results are presented for a small-scaled inverter (nine-level) with three neutral points (four DC-link capacitors). The simulation and experimental results reflect the capability and limitation of such inverters. The results are presented at all modulation indexes operated under low and high-power factor load conditions. It is found that the linear modulation range (LMR) can be increased to full base speed even for a high-power factor load.

This paper proposes an eighteen-switch five-level inverter topology for induction motor drives, enabling an extended linear modulation range till full base speed. The power circuit consists of a conventional NPC three-level inverter and a standard two-level inverter feeding the opposite phase winding ends of an open-ended winding induction motor. The proposed inverter achieves a voltage space vector radius of 0.955V _dc and a maximum peak fundamental phase voltage of 0.637V _dc in its linear modulation range compared to a conventional five-level inverter with the corresponding figures of 0.866V _dc and 0.577V _dc respectively. This improvement arises from the fact that in the overmodulation region spanning from 0.577V _dc to 0.637V _dc , the standard five-level inverter operates in a six-step mode, resulting in the voltage space vector trace a hexagonal path producing a lower-order harmonic-rich phase voltage. The proposed power circuit effectively addresses this issue by ensuring a circular locus for the voltage space vector up to a radius of 0.955V _dc resulting in a maximum peak fundamental voltage of 0.637V _dc . Consequently, it extends the linear speed range of the motor to the full base speed without lower-order harmonic problems.