This letter presents a new strategy for the formation of continuous Cu seed layer in high aspect ratio (HAR) through-silicon-vias (TSVs) with large depth based on sequential sputtering and electroless plating. The deposited seed layer is continuous and dense even at the bottom of the TSVs, which is difficult to achieve by individual sputtering or electroless plating. Combined with the spin coating of polyimide (PI) liner, atomic layer deposition (ALD) of TiN barrier layer, and electroplating of Cu conductor, TSVs with diameter of $9~\mu \text{m}$ and depth of $141~\mu \text{m}$ are successfully fabricated, and the aspect ratio is 15.5. The TSVs are fully filled without cracks or voids, proving the good quality of seed layers. Electrical measurements show that the minimum capacitance of a single TSV is around 145 fF, and the leakage current is about 3.4 pA at 20 V, indicating good electrical properties of the fabricated TSVs and the feasibility of the proposed fabrication flow in deep HAR TSV applications.

The coupled thermo-mechanical field analysis of three-dimensional (3D) stacked integrated circuits (ICs) is evaluated by an efficient and accurate simulation strategy that combines equivalent homogenization modeling methodology and sub-modeling technique. The thermal field is first investigated using the proposed approach, and based on which the structural field is also examined through the calculation of warpage. The utilization of sub-modeling method reveals the local temperature and warpage distributions, which is lost or ignored by the conventional homogenization method. To validate the proposed method, the simulation results of a five-layer stacked integrated circuits are compared against true 3D results of the detailed model, where the maximum deviation for temperature and warpage is as low as 1.62% and 4.89%, respectively, which are greatly improved compared to 8.23% and 7.83% using traditional homogenization method. In addition, the total computation time is reduced by 76.7% in contrast to true 3D finite element analysis (FEA) simulation. Furthermore, the impacts of through-silicon-via (TSV) geometries, underfill and μ -bump parameters on the temperature and warpage distributions are also studied to guide the design of 3D ICs with high performance and reliability.

High aspect ratio (HAR) through-silicon vias (TSVs) are in urgent need to achieve smaller keep-out zones (KOZs) and higher integration density for the miniaturization of high-performance three-dimensional (3D) integration of integrated circuits (IC), micro-electro-mechanical systems (MEMS), and other devices. In this study, HAR TSVs with a diameter of 11 μm and an aspect ratio of 10:1 are successfully fabricated in a low-cost process flow. Conformal polyimide (PI) liners are deposited using a vacuum-assisted spin coating technique, and the effects of spin coating time and speed on the deposition results are discussed. Then, continuous Cu seed layers are fabricated by sequential sputtering and ultrasound-assisted electroless plating. Additionally, void-free and seamless Cu conductors are formed by electroplating. Moreover, a semi-additive method is used to fabricate the redistribution layers (RDLs) on the insulating layers of photosensitive PI (PSPI). Notably, a plasma bombardment process is introduced to remove residual PSPI in the contact windows between RDLs and central pillars. Results show that the resistance of a single TSV from a daisy chain of 144 TSVs with density of 2000/mm² is about 28 mΩ. Additionally, the S-parameters of a single TSV are obtained using L-2L de-embedding technology, and the experimental and simulated results agree well. The proposed low-cost fabrication technologies and the related electrical characterization of PI-TSVs are significant for the application of HAR TSVs in modern heterogeneous integration systems.

Polymer liner has been used in through-silicon-vias (TSVs) for smaller parasitic capacitance and better thermo-mechanical performance. For the application in heterogeneous integrated systems, it is critical to study the thermal reliability of such TSVs in both theoretical modeling and experimental characterization. Among the numerous reliability challenges, the Cu protrusion phenomenon of TSVs is one of the most severe issues, which can lead to cracks and delamination in integrated systems. In this article, the annealing-induced Cu protrusion of polyimide (PI) liner TSVs is studied by experiments and simulations. PI-TSVs are fabricated and the Cu protrusion at various annealing conditions is characterized. Finite element analysis (FEA) is carefully carried out taking into account the diffusion creep rate model, and the deviations between FEA and experiment results of protrusion heights are less than 3%. Besides, the deformation procedure and the creep behavior of Cu pillars during annealing are analyzed. Based on the proposed FEA model, comprehensive parametric analyses are conducted to study the effects of different annealing conditions on the Cu protrusion heights, which are helpful to understand and improve the thermal reliability of PI-TSVs.

Microgrippers are essential for assembly and manipulation at the micro- and nano-scales, facilitating important applications in microelectronics, MEMS, and biomedical engineering. To guarantee the safe handling of delicate materials and micro-objects, a microgripper needs to be designed to operate with exceptional precision, rapid response, user-friendly operation, strong reliability, and low power consumption. In this study, we develop an electrothermal actuated microgripper with Al-SiO₂ bimorphs as the primary structural element. The fabricated microgripper naturally adopts a closed state due to process-induced residual stresses. The thermal expansion mismatch between Al and SiO₂ allows for an easy transition of the microgripper between open and closed states by temperature control. Experimental data reveal that the microgripper can achieve impressive deformability, bending over 100 degrees at just 5 V, and responding within 10 ms. Its capability to handle micro-objects is verified using polymethyl methacrylate (PMMA) microbeads and its gripping strength is quantitatively assessed. It is demonstrated that the microgripper holding a microbead with a diameter of 400 μm and a weight of 0.1 mg can withstand an average acceleration of 35 g during vibration test and over 1600 g in impact tests, highlighting its exceptional grasping performance. Additionally, the “pick-and-place” task for handling and positioning solder beads (0.25 mg for each bead) with diameters of 400 μm on a bulk silicon inductor chip has been successfully completed. This unique microgripper is anticipated to be highly beneficial for various micro-assembly and micromanipulation applications, particularly in the field of electronic packaging.

Silicon interposers embedded with ultra-deep through-silicon vias (TSVs) are in great demand for the heterogeneous integration and packaging of opto-electronic chiplets and microelectromechanical systems (MEMS) devices. Considering the cost-effective and reliable manufacturing of ultra-deep TSVs, the formation of continuous barrier and seed layers remains a crucial challenge to solve. Herein, we present a novel dual catalysis-based electroless plating (ELP) technique by tailoring polyimide (PI) liner surfaces to fabricate dense combined Ni barrier/seed layers in ultra-deep TSVs. In additional to the conventional acid catalysis procedure, a prior catalytic step in an alkaline environment is proposed to hydrolyze the PI surface into a polyamide acid (PAA) interfacial layer, resulting in additional catalysts and the formation of a dense Ni layer that can function as both a barrier layer and a seed layer, particularly at the bottom of the deep TSV. TSVs with depths larger than 500 μm and no voids are successfully fabricated in this study. The fabrication process involves low costs and temperatures. For a fabricated 530-μm-deep TSV with a diameter of 70 μm, the measured depletion capacitance and leakage current are approximately 1.3 pF and 1.7 pA at 20 V, respectively, indicating good electrical properties. The proposed fabrication strategy can provide a cost-effective and feasible solution to the challenge of manufacturing ultra-deep TSVs for modern 3D heterogeneous integration and packaging applications.