In the past few decades, NAND flash memory has been one of the most successful nonvolatile storage technologies, and it is commonly used in electronic devices because of its high scalability and reliable switching properties. To overcome the scaling limit of planar NAND flash arrays, various three-dimensional (3D) architectures of NAND flash memory and their process integration methods have been investigated in both industry and academia and adopted in commercial mass production. In this paper, 3D NAND flash technologies are reviewed in terms of their architecture and fabrication methods, and the advantages and disadvantages of the architectures are compared.

In this article, a 5-nm node two-stack nanosheet FET with a triple-k spacer structure representing three spacer regions consisting of two inner spacers (inner spacer 1 and inner spacer 2) formed by two atomic layer deposition (ALD) processes leveraging the inner spacer formation-process method and outer spacer process of stack gate-all-around (GAA) process is proposed. Material and structure optimization was performed to confirm the effects of each spacer regions. Inner spacer 1 has a direct effect on the channel extension region. However, the inner spacer 2 is not in direct contact with the channel extension region and the gate, thus confirming the relatively indirect effect. In addition, the material dependence of the outer spacer, formed between the gate and the side region of the channel where the field is concentrated, was confirmed. By comparing the optimized triple-k spacer structure with the fully nitride spacer, the improved dynamic performance, as well as the active power and static power, was identified.

In this work, we present a hardware neural network with capacitor-based synaptic devices. A capacitor-based synaptic device was developed using a MOS capacitor structure with a charge trapping layer. Due to the flat band voltage shift by charge trapping and its non-linear ${C} - {V}$ characteristics, multilevel weight values could be implemented by the charge occurring when charging and discharging the capacitor. The vector-matrix multiplication (VMM) function was also experimentally verified using a fabricated synapse array based on NAND flash structure.

In this article, structure optimization of high-k interfacial layer (IL), deposited between the gate and the gate sidewall spacer, was performed in a 5-nm node nanosheet field-effect transistor (NSFET). High-k IL can be formed during the high-k gate dielectric and metal gate (HKMG) with gate-last process. By optimizing the structure of thickness of high-k IL (Thk) with gate length (LG), spacer length (Lext), and source/drain (S/D) length (LS/D), improved electrical performances were obtained. By optimizing Thk with properly adjusted LG, Lext, and LS/D, highly saturated on-/off-current ratio (Ion/Ioff) was obtained with appropriate drain-induced barrier lowering (DIBL). Besides, reduced intrinsic gate delay (Cgg) properties and off-state leakage current were identified. In addition, the reason of increased off-state leakage, which can be shown when Lext shrinks with extending Thk, was also investigated. Finally, the optimized electrical characteristics were obtained when Thk is adjusted with LG and LS/D. The power was reduced about 27% with the same performance and 18% enhanced performance was obtained when Thk is optimized through LG. On the contrary, reduced off-state leakage current and DIBL were confirmed in the case of optimization point with LS/D, which result in lower static power. Based on this comparison, optimization method and guideline for high-k IL was proposed.

Ferroelectric field-effect transistor (FeFET) can be operated as a nonvolatile memory device with low programming voltage based on polarization. In particular, it can be used as a synaptic device in a neuromorphic system based on the nand flash array structure. We demonstrate a Hf $_\text{0.5}$ Zr $_\text{0.5}$ O $_\text{2}$ (HZO)-based FeFET device fabricated on a silicon-on-insulator (SOI) substrate with high on/off ratio and reliability characteristics. The HZO-based FeFET is utilized as a synaptic device based on the 3-D nand architecture. It is verified with the binarization of input–output signals and weight value for efficient vector–matrix multiplication (VMM) operation using the 3-D nand architecture. In addition, a neural network layer-mapping method increasing synaptic cell efficiency is proposed. A system-level simulation is performed based on the FeFET single-device experimental data. The VMM operation is verified through the SPICE Berkeley short-channel IGFET model (BSIM), and off-chip ( ex-situ ) learning with binary neural network (BNN) is performed for the Modified National Institute of Standards and Technology Database MNIST and fashion-MNIST data. The results confirm that the proposed FeFET-based BNN can perform accurate VMM operations and is robust to variations due to the binary weight state.

As the computing paradigm has shifted toward edge computing, improving the security of edge devices is attracting significant attention. However, because edge devices have limited resources in terms of power and area, it is difficult to apply a conventional cryptography system to protect them. On the other hand, as a simple security application, a physical unclonable function (PUF) can be implemented without power and area problems because it provides a security key by utilizing process variations without additional external circuits. Ferroelectric tunnel junctions (FTJs) are 2-terminal devices that store information by changing the resistance of a ferroelectric material, where the resistance is determined by the polarization states of the ferroelectric domains. Because polycrystalline ferroelectric materials have a multi-domain nature, domain variation can also be used as a randomness source to induce cell-to-cell variations along with process variations. In this paper, we demonstrate PUF operations of a low-power, small area 16 × 16 hafnium oxide (pure-HfO _x )-based FTJ array using certain metrics. It is clear that the proposed array consisting of scaled FTJs has adequate randomness for security applications such that the array-level PUF operations are robust against model-based machine learning attacks.