Over the last decade, gallium nitride (GaN) has emerged as an excellent material for the fabrication of power devices. Among the semiconductors for which power devices are already available in the market, GaN has the widest energy gap, the largest critical field, and the highest saturation velocity, thus representing an excellent material for the fabrication of high-speed/high-voltage components. The presence of spontaneous and piezoelectric polarization allows us to create a two-dimensional electron gas, with high mobility and large channel density, in the absence of any doping, thanks to the use of AlGaN/GaN heterostructures. This contributes to minimize resistive losses; at the same time, for GaN transistors, switching losses are very low, thanks to the small parasitic capacitances and switching charges. Device scaling and monolithic integration enable a high-frequency operation, with consequent advantages in terms of miniaturization. For high power/high-voltage operation, vertical device architectures are being proposed and investigated, and three-dimensional structures—fin-shaped, trench-structured, nanowire-based—are demonstrating great potential. Contrary to Si, GaN is a relatively young material: trapping and degradation processes must be understood and described in detail, with the aim of optimizing device stability and reliability. This Tutorial describes the physics, technology, and reliability of GaN-based power devices: in the first part of the article, starting from a discussion of the main properties of the material, the characteristics of lateral and vertical GaN transistors are discussed in detail to provide guidance in this complex and interesting field. The second part of the paper focuses on trapping and reliability aspects: the physical origin of traps in GaN and the main degradation mechanisms are discussed in detail. The wide set of referenced papers and the insight into the most relevant aspects gives the reader a comprehensive overview on the present and next-generation GaN electronics.

Various large-area growth methods for two-dimensional transition metal dichalcogenides have been developed recently for future electronic and photonic applications. However, they have not yet been employed for synthesizing active pixel image sensors. Here, we report on an active pixel image sensor array with a bilayer MoS₂ film prepared via a two-step large-area growth method. The active pixel of image sensor is composed of 2D MoS₂ switching transistors and 2D MoS₂ phototransistors. The maximum photoresponsivity (R_ph) of the bilayer MoS₂ phototransistors in an 8 × 8 active pixel image sensor array is statistically measured as high as 119.16 A W⁻¹. With the aid of computational modeling, we find that the main mechanism for the high R_ph of the bilayer MoS₂ phototransistor is a photo-gating effect by the holes trapped at subgap states. The image-sensing characteristics of the bilayer MoS₂ active pixel image sensor array are successfully investigated using light stencil projection.

Ferroelectric transistors (FeFETs) based on doped hafnium oxide (HfO $_{\text{2}}$ ) have received much attention due to their technological potential in terms of scalability, high-speed, and low-power operation. Unfortunately, however, HfO $_{\text{2}}$ -FeFETs also suffer from persistent reliability challenges, specifically affecting retention, endurance, and variability. A deep understanding of the reliability physics of HfO $_{\text{2}}$ -FeFETs is an essential prerequisite for the successful commercialization of this promising technology. In this article, we review the literature about the relevant reliability aspects of HfO $_{\text{2}}$ -FeFETs. We initially focus on the reliability physics of ferroelectric capacitors, as a prelude to a comprehensive analysis of FeFET reliability. Then, we interpret key reliability metrics of the FeFET at the device level (i.e., retention, endurance, and variability) based on the physical mechanisms previously identified. Finally, we discuss the implications of device-level reliability metrics at both the circuit and system levels. Our integrative approach connects apparently unrelated reliability issues and suggests mitigation strategies at the device, circuit, or system level. We conclude this article by proposing a set of research opportunities to guide future development in this field.

In this paper, we report about the derivation of a physics-based compact model of random telegraph noise (RTN) in HfO₂-based resistive random access memory (RRAM) devices. Starting from the physics of charge transport, which is different in the high resistive states and low resistive states, we explore the mechanisms responsible for RTN exploiting a hybrid approach, based on self-consistent physics simulations and geometrical simplifications. Then, we develop a simple yet effective physics-based compact model of RTN valid in both states, which can be steadily integrated in state-of-the-art RRAM compact models. The RTN compact model predictions are validated by comparison with both a large experimental data set obtained by measuring RRAM devices in different conditions, and data reported in the literature. In addition, we show how the model enables advanced circuit simulations by exploring three different circuits for memory, security, and logic applications.

Dynamic $R_{{on}}$ dispersion due to buffer traps is a well-known issue of GaN power high electron mobility transistors (HEMTs), critically impacting their performance and stability. Several works show that the dynamic $R_{{on}}$ reaches a maximum for some off-state drain-source voltage ( $V_{DS,{off}}$ ) value typically in the range of several hundred volts and then partially recovers to smaller values. In this work, we propose a quantitative explanation for this behavior, attributing it to the charging/discharging dynamics of carbon (C)-related buffer traps. We characterize the dynamic $R_{{on}}$ in packaged p-GaN gate AlGaN/GaN HEMTs with a custom measurement setup. We find that in these devices, the relative $R_{{on}}$ increase reaches a maximum of 60% for $V_{DS,{off}} ≈ 100$ -200 V, partially recovering to about 30% as $V_{DS,{off}}$ is raised to 500 V. We ascribe this behavior to the partial neutralization of C-related acceptor traps in the buffer due to trapping of holes produced by a high-field generation mechanism. This explanation is supported by calibrated 2-D numerical simulations, that successfully reproduce the experimentally observed $R_{{on}}$ reduction only when including a hole generation mechanism.

RON degradation due to stress in GaN-based power devices is a critical issue that limits, among other effects, long-term stable operation. Here, by means of 2-D device simulations, we show that the RON increase and decrease during stress and recovery experiments in carbon-doped AlGaN/GaN power metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) can be explained with a model based on the emission, redistribution, and retrapping of holes within the carbon-doped buffer (``hole redistribution'' in short). By comparing simulation results with front- and back-gating OFF-state stress experiments, we provide an explanation for the puzzling observation of both stress and recovery transients being thermally activated with the same activation energy of about 0.9 eV. This finds a straightforward justification in a model in which both RON degradation and recovery processes are limited by hole emission by dominant carbon-related acceptors that are energetically located at about 0.9 eV from the GaN valence band.