This article presents a neural-recording IC with automatic gain control (AGC) according to the input signal level. AGC enhances the dynamic range (DR) of the recording IC by more than 30 dB and allows it to take the benefits of the front-end amplification-based and direct-conversion-based recording structures concurrently. By adaptively controlling the analog front-end (AFE) gain, the input-referred noise (IRN) of the overall system is greatly reduced while ensuring a wide DR. A continuous-time (CT) dynamic-zoom $\Delta \Sigma $ ADC (CT-Zoom-ADC) is used for power-efficient two-step conversion. The coarse conversion output is reused for AGC, and the fine conversion resolution is adjusted adaptively by modifying the oversampling ratio according to the varying AFE gain. The presented neural-recording IC achieves 99.5-dB DR and 6.1- $\mu \text{V}_{\textrm {rms}}$ IRN over 5-kHz bandwidth, resulting in FoM _DR of 185.2 dB, the effective number of bits (ENOB) of 11.4 bits, and tolerance against artifacts with differential voltage amplitudes up to 1.6 $\text{V}_{\text {pp}}$ . Measurements with pulsatile artifacts and experiments in vivo validate that the proposed IC is applicable to the closed-loop neural interface.

In this letter, we present a multibit static random-access memory computing-in-memory (CIM) macro with enhanced energy efficiency for edge devices tasking machine learning (ML) deep neural networks (DNNs). The proposed CIM macro computes matrix-vector multiplications (MVM) in an efficient “one-step” method reducing the energy consumption and control complexity. Furthermore, the proposed method computes not only the multiplications of a single weight but also the multibit weight with bit-shifting in the charge domain without the use of additional CMOS switches, thereby achieving very high energy efficiency. Measurement results in a 65-nm CMOS prototype chip show that it achieves the highest throughput of 204.8 GOPS at 1.2 V and 133.6 TOPS/W at 0.85 V.

This work presents a 4 kb 8T-SRAM computation-in-memory (CIM) macro based on hybrid computation using digital in-memory-array computing (DIMAC) and phase-domain near-memory-array computing (PNMAC). By employing multiple local dual-column arrays (LDCAs), bit-wise multiplications are computed digitally in memory with high energy efficiency and throughput. The PNMAC performs the summation and accumulation in parallel with a high dynamic range by using a proposed steering-DAC-based differential current-controlled-oscillator (DCCO). After the phase-domain accumulation is completed, only a one-time digital conversion needs to be performed using a phase quantizer with negligible phase-to-digital conversion overhead. Moreover, by effectively reusing the steered current to accumulate the multiplication results fed from the DIMAC, the power consumption of the PNMAC can be greatly reduced. The macro fabricated in a 65 nm process achieves 22.4TOPS/W peak energy efficiency and $19.03~\mu \text{W}$ power consumption with a 59.8% zero-skipping rate, which is $96.05\times $ lower than state of the art.

This article presents an ultrasound (US) transceiver IC including a highly power-efficient US receiver (RX) and a high-voltage (HV) US transmitter (TX) for US capsule endoscopy (USCE) systems for the first time. The proposed USCE system employs the developed IC, a single-element piezoelectric transducer (PZT), and a mechanically rotating reflector to obtain 360 $^{\circ}$ transmural scans while traveling through the gastrointestinal (GI) tract. Since the USCE system operates with a tiny battery, power efficiency is greatly important. To reduce power consumption by decreasing the required operating speed of the analog-to-digital converter (ADC), we propose a new RX structure employing synchronized analog envelope detection. It is unlike conventional US RX ICs that necessitate power-hungry high-speed ADCs to acquire the US signal residing at a high center frequency with wide bandwidth. Instead, the proposed work employs an analog envelope detector based on a quadrature demodulation method. As a result, it uses only a single circuit path rather than two (I and Q) paths by using a demodulation carrier whose phase is synchronized with the incoming US signal. A ping-pong noise-shaping (NS) SAR ADC is adopted to improve resolution while maintaining low power consumption. Besides, the TX IC, including an on-chip charge pump, is designed to generate HV pulses to drive the PZT. The prototype IC is fabricated in a 0.18 $\mu$ m bipolar-CMOS-DMOS (BCD) process. The RX consumes 2.3 mW, and the ADC achieves a 53.71 dB SNDR and a 66.45 dB SFDR. The TX generates 25 V pulses with 25 ns pulsewidth. US B-mode images of a water tank and a custom phantom are successfully obtained by using the prototype capsule endoscopy system employing the fabricated IC chip.

In analog-mixed-signal (AMS) compute-in-memory (CIM) systems, the two’s-complement (2SC) format provides better area efficiency than the sign-and-magnitude (SNM) one. However, the 2SC format exacerbates the challenges of AMS-CIM systems, suffering from significant DNN accuracy drop under process variations and high computation currents from activating multiple WLs. In the 2SC format‘, 0’ and ‘1’ are nearly balanced for all logical-order bits, unlike ‘0’-skewed higher-order bits in the SNM format. Consequently, the 2SC-based AMS-CIM systems have much more on-cells than the SNM-based counterpart, deteriorating the above challenges. We propose Skew-CIM, a software-hardware co-design technique to relax these challenges. Our proposed weight skewing (WESK) breaks the ‘0’ and ‘1’ balance at the software level. The potential accuracy drops resulting from WESK are successfully compensated by retraining DNNs. The offsets caused by WESK can be easily corrected using online hardware-level processing. Our Skew-CIM technique can be applied to most AMS-CIM systems with memories showing large on-off cell current ratios. As an example, we use it in a custom-designed 8T-SRAM-based CIM device, demonstrating a significant reduction in the DNN classification error by 7.6 times compared to the 2SC-based AMS-CIM without our Skew-CIM technique. Furthermore, our Skew-CIM markedly enhances energy efficiency by up to 39.9%, outperforming conventional SNM-based AMS-CIM systems.

Radiation sensor interfaces for battery-powered mobile dosimeters must consume low power to monitor the amount of radiation exposure over a long period. This paper proposes a power-efficient radiation sensor interface using a peak-triggered sampling scheme. Since the peak of the analog-to-digital converter’s (ADC’s) input represents radiation energy, our ADC only operates around the peak value thanks to the proposed sampling scheme. Although our ADC operates with a high sampling frequency, this proposed sampling scheme reduces the power consumption of the sensor interface because of the reduced operation time of the ADC. Our sensor interface does not have signal distortion caused by a conventional shaper because the interface quantizes the peak value using the high sampling frequency instead of the shaper. When the radiation input occurs once every 10 μs, the power consumption of the ADC with the proposed sampling scheme is only about 21.5% of the ADC’s power consumption when the ADC continuously operates. In this worst case, the fabricated radiation sensor interface in a 0.18-μm complementary metal-oxide-semiconductor (CMOS) process consumes only 1.11 mW.