This paper reviews architectures and circuit implementations of on-chip sinusoidal signal generators (SSGs) for electrical impedance spectroscopy (EIS) applications. In recent years, there have been increasing interests in on-chip EIS systems, which measure a target material’s impedance spectrum over a frequency range. The on-chip implementation allows EIS systems to have low power and small form factor, enabling various biomedical applications. One of the key building blocks of on-chip EIS systems is on-chip SSG, which determines the frequency range and the analysis precision of the whole EIS system. On-chip SSGs are generally required to have high linearity, wide frequency range, and high power and area efficiency. They are typically composed of three stages in general: waveform generation, linearity enhancement, and current injection. First, a sinusoidal waveform should be generated in SSGs. The generated waveform’s frequency should be accurately adjustable over a wide range. The firstly generated waveform may not be perfectly linear, including unwanted harmonics. In the following linearity-enhancement step, these harmonics are attenuated by using filters typically. As the linearity of the waveform is improved, the precision of the EIS system gets ensured. Lastly, the filtered voltage waveform is now converted to a current by a current driver. Then, the current sinusoidal signal is injected into the target impedance. This review discusses the principles, advantages, and disadvantages of various techniques applied to each step in state-of-the-art on-chip SSGs. In addition, state-of-the-art designs are compared and summarized.

This article presents a neural-recording IC with automatic gain control (AGC) according to the input signal level. AGC enhances the dynamic range (DR) of the recording IC by more than 30 dB and allows it to take the benefits of the front-end amplification-based and direct-conversion-based recording structures concurrently. By adaptively controlling the analog front-end (AFE) gain, the input-referred noise (IRN) of the overall system is greatly reduced while ensuring a wide DR. A continuous-time (CT) dynamic-zoom $\Delta \Sigma $ ADC (CT-Zoom-ADC) is used for power-efficient two-step conversion. The coarse conversion output is reused for AGC, and the fine conversion resolution is adjusted adaptively by modifying the oversampling ratio according to the varying AFE gain. The presented neural-recording IC achieves 99.5-dB DR and 6.1- $\mu \text{V}_{\textrm {rms}}$ IRN over 5-kHz bandwidth, resulting in FoM _DR of 185.2 dB, the effective number of bits (ENOB) of 11.4 bits, and tolerance against artifacts with differential voltage amplitudes up to 1.6 $\text{V}_{\text {pp}}$ . Measurements with pulsatile artifacts and experiments in vivo validate that the proposed IC is applicable to the closed-loop neural interface.

This review article provides a comprehensive overview of impedance-readout integrated circuits (ICs) for electrical impedance spectroscopy (EIS) applications. The readout IC, a crucial component of on-chip EIS systems, significantly affects key performance metrics of the entire system, such as frequency range, power consumption, accuracy, detection range, and throughput. With the growing demand for portable, wearable, and implantable EIS systems in the Internet-of-Things (IoT) era, achieving high energy efficiency while maintaining a wide frequency range, high accuracy, wide dynamic range, and high throughput has become a focus of research. Furthermore, to enhance the miniaturization and convenience of EIS systems, many emerging systems utilize two-electrode or dry electrode configurations instead of the conventional four-electrode configuration with wet electrodes for impedance measurement. In response to these trends, various technologies have been developed to ensure reliable operations even at two- or dry-electrode interfaces. This article reviews the principles, advantages, and disadvantages of techniques employed in state-of-the-art impedance-readout ICs, aiming to achieve high energy efficiency, wide frequency range, high accuracy, wide dynamic range, low noise, high throughput, and/or high input impedance. The thorough review of these advancements will provide valuable insights into the future development of impedance-readout ICs and systems for IoT and biomedical applications.

This paper presents a wireless and wearable body-pressure-monitoring system for the on-site, real-time prevention of pressure injuries for immobilized patients. For the prevention of pressure-induced skin injuries, a wearable pressure sensor system is designed to monitor the pressure at multiple sites on the skin and to alert the danger of prolonged application of pressure on the skin with a pressure-time integral (PTI) algorithm. The wearable sensor unit is developed using a pressure sensor based on a liquid metal microchannel and integrated with a flexible printed circuit board that includes a thermistor-type temperature sensor. The wearable sensor unit array is connected to the readout system board for the transmission of measured signals to a mobile device or PC via Bluetooth communication. We evaluate the pressure-sensing performances of the sensor unit and the feasibility of the wireless and wearable body-pressure-monitoring system through an indoor test and a preliminary clinical test at the hospital. It is shown that the presented pressure sensor has high-quality performance with excellent sensitivity to detect both high and low pressure. The proposed system measures the pressure at bony sites on the skin for about six hours continuously without any disconnection or failure, and the PTI-based alarming system operates successfully in the clinical setup. The system measures the pressure applied to the patient and provides meaningful information from the measured data for early diagnosis and prevention of bedsores to doctors, nurses, and healthcare workers.

This paper presents an error-tolerant and power-efficient impedance measurement scheme for bioimpedance acquisition. The proposed architecture measures the magnitude and the real part of the target complex impedance, unlike other impedance measurement architectures measuring either the real/imaginary components or the magnitude and phase. The phase information of the target impedance is obtained by using the ratio between the magnitude and the real components. This can allow for avoiding direct phase measurements, which require fast, power-hungry circuit blocks. A reference resistor is connected in series with the target impedance to compensate for the errors caused by the delay in the sinusoidal signal generator and the amplifier at the front. Moreover, an additional magnitude measurement path is connected to the reference resistor to cancel out the nonlinearity of the proposed system and enhance the settling speed of the low-pass filter by a ratio-based detection. Thanks to this ratio-based detection, the accuracy is enhanced by 30%, and the settling time is improved by 87.7% compared to the conventional single-path detection. The proposed integrated circuit consumes only 513 $\mathsf{\mu }$W for a wide frequency range of 10 Hz to 1 MHz, with the maximum magnitude and phase errors of 0.3% and 2.1$°$, respectively.

In this paper, we present a new impedance measurement integrated circuit (IC) for achieving a wideband coverage up to 10 MHz and low power consumption. A frequency-shift technique is applied to down-shift the input frequency, which ranges from 100 kHz to 10 MHz, into an intermediate frequency of 10 kHz, while the frequency-shifting is bypassed when the input frequency falls in the range from 100 Hz to 100 kHz. It results in 100 times relaxation of the requirement on the instrumentation amplifier (IA) bandwidth and the comparator delay, greatly reducing overall power consumption. The proposed IC employs the polar demodulation structure with a reference resistor that provides reference timing information avoiding any synchronization issue with the transmitter. In order to compensate for the comparator delay and nonlinearity of the IA, the reference magnitude measurement path is added, making only the mismatch of the circuit affects the accuracy. This allows for employing the auto-zeroing technique that can remove the offset but increase the absolute delay by using an additional capacitor to the comparator. The chip fabricated in a 0.18- $\mu$ m CMOS technology consumes the power of 756 $\mu$ W while covering the measurement frequency range from 100 Hz to 10 MHz and exhibiting the maximum magnitude and phase errors of 1.1 $\%$ and 1.9 $^{\circ }$ , respectively.