This paper reports a linear multiply-accumulate (MAC) operation conducted on a crossbar memory array based on 28nm high-k metal gate (HKMG) Complementary Metal Oxide Semiconductor (CMOS) and ferroelectric field effect transistor (FeFET). The fabrication is conducted at GlobalFoundries with their standard 28nm technology. The crossbar arrays show a 100% yield in MAC operation on a 300mm wafer. The arrays were divided into 8×8 segments. The FeFET crossbar arrays were fabricated with access transistors, current-limiter transistors and a current-mode analog-to-digital converter (ADC) on the same wafer. Finally, the data retention characteristics reveal excellent data retention characteristics up to 5×10 ⁴ seconds, which makes this memory array suitable for carrying out MAC operations in inference engine applications.

This paper reports 2bits/cell ferroelectric FET (FeFET) devices with 500 ns write pulse of maximum amplitude 4.5V for inference-engine applications. FeFET devices were fabricated using GlobalFoundries 28nm high-k-metal-gate (HKMG) process flow on a 300mm wafer. The devices were characterized, and statistical modeling of variations in the fabricated devices was carried out based on experimental data. Furthermore, the model was applied to multi-layer perceptron (MLP) neural network (NN) simulations using the CIMulator software platform. The neural network (NN) was trained offline, and the weights were transferred to the synaptic devices for an inference-only operation. Device-to-device (D2D) and cycle-to-cycle (C2C) variations are limited by optimal process conditions and do not impact inference accuracy. However, due to short-term retention, read-to-read (R2R) variation significantly affects inference operation. This work proposes a synergistic READ -optimization approach to mitigate the impact of short-term retention and device variation issues. The optimization technique fostered immunity in the MLP-NN towards R2R variations, and the MLP-NN maintains inference accuracy of 97.01%, while the software baseline is 98%.

This article reports a novel ferroelectric field-effect transistor (FeFET)-based crossbar array cascaded with an external resistor. The external resistor is shunted with the column of the FeFET array, as a current limiter and reduces the impact of variations in drain current ( $\textit{I}_{\textit{d}}$ ), especially in a low threshold voltage (LVT) state. We have designed crossbar arrays of 8 $\times$ 8 sizes and performed multiply-and-accumulate (MAC) operations. Furthermore, we have evaluated the performance of the current limited FeFET crossbar array in system-level applications. Finally, the system-level performance evaluation was done by neuromorphic simulation of the resistor-shunted FeFET crossbar array. The crossbar array achieved software-comparable inference accuracy ( $\sim$ 97%) for National Institute of Standards and Technology (MNIST) datasets with multilayer perceptron (MLP) neural network, whereas the crossbar arrays built solely with FeFETs failed to learn, yielding only 9.8% accuracy.

This work presents 2-bits/cell operation in deeply scaled ferroelectric finFETs (Fe-finFET) with a 1 µs write pulse of maximum ±5 V amplitude and WRITE endurance above 10⁹ cycles. Fe-finFET devices with single and multiple fins have been fabricated on an SOI wafer using a gate first process, with gate lengths down to 70 nm and fin width 20 nm. Extrapolated retention above 10 years also ensures stable inference operation for 10 years without any need for re-training. Statistical modeling of device-to-device and cycle-to-cycle variation is performed based on measured data and applied to neural network simulations using the CIMulator software platform. Stochastic device-to-device variation is mainly compensated during online training and has virtually no impact on training accuracy. On the other hand, stochastic cycle-to-cycle threshold voltage variation up to 400 mV can be tolerated for MNIST handwritten digits recognition. A substantial inference accuracy drop with systematic retention degradation was observed in analog neural networks. However, quaternary neural networks (QNNs) and binary neural networks (BNNs) with Fe-finFETs as synaptic devices demonstrated excellent immunity toward the cumulative impact of stochastic and systematic variations.

This article reports an improvement in the performance of the hafnium oxide-based (HfO₂) ferroelectric field-effect transistors (FeFET) achieved by a synergistic approach of interfacial layer (IL) engineering and READ-voltage optimization. FeFET devices with silicon dioxide (SiO₂) and silicon oxynitride (SiON) as IL were fabricated and characterized. Although the FeFETs with SiO₂ interfaces demonstrated better low-frequency characteristics compared to the FeFETs with SiON interfaces, the latter demonstrated better WRITE endurance and retention. Finally, the neuromorphic simulation was conducted to evaluate the performance of FeFETs with SiO₂ and SiON IL as synaptic devices. We observed that the WRITE endurance in both types of FeFETs was insufficient to carry out online neural network training. Therefore, we consider an inference-only operation with offline neural network training. The system-level simulation reveals that the impact of systematic degradation via retention degradation is much more significant for inference-only operation than low-frequency noise. The neural network with FeFETs based on SiON IL in the synaptic core shows 96% accuracy for the inference operation on the handwritten digit from the Modified National Institute of Standards and Technology (MNIST) data set in the presence of flicker noise and retention degradation, which is only a 2.5% deviation from the software baseline.