A CMOS (Complementary metal-oxide-semiconductor) Hall sensor with low power consumption and simple structure is introduced. The tiny magnetic signal from Hall device could be detected by a high-resolution delta-sigma ADC in presence of offset and flickering noise. Also, the offset as well as the flickering noise are effectively suppressed by the current spinning technique combined with double sampling switches of the ADC. The double sampling scheme of the ADC reduces the operating frequency and helps to reduce the power consumption. The prototype Hall sensor is fabricated in a 0.18-µm CMOS process, and the measurement shows detection range of ±150 mT and sensitivity of 110 µV/mT. The size of active area is 0.7 mm², and the total power consumption is 4.9 mW. The proposed system is advantageous not only for low power consumption, but also for small sensor size due to its simplicity.

This paper presents a small-sized, low-power gas sensor system combining a high-electron-mobility transistor (HEMT) device and readout integrated circuit (ROIC). Using a semiconductor-based HEMT as a gas-sensing device, it is possible to secure high sensitivity, reduced complexity, low power, and small size of the ROIC sensor system. Unlike existing gas sensors comprising only HEMT elements, the proposed sensor system has both an ROIC and a digital controller and can control sensor operation through a simple calibration process with digital signal processing while maintaining constant performance despite variations. The ROIC mainly consists of a transimpedance amplifier (TIA), a negative-voltage generator, and an analog-to-digital converter (ADC) and is designed to match a minimum target detection unit of 1 ppm for hydrogen. The prototype ROIC for the HEMT presented herein was implemented in a 0.18 µm complementary metal–oxide–semiconductor (CMOS) process. The total measured power consumption and detection unit of the proposed ROIC for hydrogen gas were 3.1 mW and 2.6 ppm, respectively.

This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter. This consequently achieves the high-power efficiency of the ADC. The simulated SNDR is 79.97 dB; it achieves a 12.5-MHz BW at a 175-MHz sampling rate, with OSR of 7. The total power consumption of the ADC is 4.27 mW at a 1.1-V supply. The ${\mathrm{FoM}}_{\mathrm{S},\mathrm{SNDR}}$ is 174.6 dB. The proposed structure achieves high resolution and wide bandwidth with good energy efficiency.

In this study, a pipelined noise-shaping successive-approximation register analog-to-digital converter (PLNS-SAR ADC) structure was proposed to achieve high resolution and to be free from comparator design requirements. The inter-stage amplifier and integrator of the PLNS-SAR ADC were implemented through a ring amplifier with high gain and speed. The ring amplifier was designed to improve power efficiency and be tolerant to process–voltage–temperature (PVT) variation, and uses a single loop common-mode feedback (CMFB) circuit. By processing residual signals with a single ring amplifier, power efficiency can be maximized, and a low-power system with 30% lower power consumption than that of a conventional PLNS-SAR ADC is implemented. With a high-gain ring amplifier, noise leakage is greatly suppressed, and a structure can be implemented that is tolerant of mismatches between the analog loop and digital correction filters. The measured signal to noise distortion ratio (SNDR) is 70 dB for a 5.15 MHz bandwidth (BW) at a 72 MS/s sampling rate (Fs) with an oversampling ratio (OSR) of 7, and the power consumption is 2.4 mW. The ${\mathrm{FoM}}_{\mathrm{S},\mathrm{SNDR}}$ (= SNDR + ${10\log }_{10}$BW/Power) is 163.5 dB. The proposed structure in this study can achieve high resolution and wide BW with good power efficiency, without a filter calibration process, through the use of a ring amplifier in the PLNS-SAR ADC.